stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332317 # Number of seconds simulated 4sim_ticks 2332316587000 # Number of ticks simulated 5final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2072038 # Simulator instruction rate (inst/s) 8host_tick_rate 63144661085 # Simulator tick rate (ticks/s) 9host_mem_usage 379208 # Number of bytes of host memory used 10host_seconds 36.94 # Real time elapsed on the host 11sim_insts 76532931 # Number of instructions simulated 12system.nvmem.bytes_read 20 # Number of bytes read from this memory 13system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 14system.nvmem.bytes_written 0 # Number of bytes written to this memory 15system.nvmem.num_reads 5 # Number of read requests responded to by this memory 16system.nvmem.num_writes 0 # Number of write requests responded to by this memory 17system.nvmem.num_other 0 # Number of other requests responded to by this memory 18system.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) 19system.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) 20system.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) 21system.physmem.bytes_read 122663536 # Number of bytes read from this memory 22system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory 23system.physmem.bytes_written 9577800 # Number of bytes written to this memory 24system.physmem.num_reads 14137126 # Number of read requests responded to by this memory 25system.physmem.num_writes 856485 # Number of write requests responded to by this memory 26system.physmem.num_other 0 # Number of other requests responded to by this memory 27system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s) 30system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s) 31system.l2c.replacements 116822 # number of replacements 32system.l2c.tagsinuse 24240.388378 # Cycle average of tags in use 33system.l2c.total_refs 1520830 # Total number of references to valid blocks. 34system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. 35system.l2c.avg_refs 10.356562 # Average number of references to valid blocks. 36system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 37system.l2c.occ_blocks::0 10591.091336 # Average occupied blocks per context 38system.l2c.occ_blocks::1 13649.297042 # Average occupied blocks per context 39system.l2c.occ_percent::0 0.161607 # Average percentage of cache occupancy 40system.l2c.occ_percent::1 0.208272 # Average percentage of cache occupancy 41system.l2c.ReadReq_hits::0 1188216 # number of ReadReq hits 42system.l2c.ReadReq_hits::1 10669 # number of ReadReq hits 43system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits 44system.l2c.Writeback_hits::0 604613 # number of Writeback hits 45system.l2c.Writeback_hits::total 604613 # number of Writeback hits 46system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits 47system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits 48system.l2c.ReadExReq_hits::0 105791 # number of ReadExReq hits 49system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits 50system.l2c.demand_hits::0 1294007 # number of demand (read+write) hits 51system.l2c.demand_hits::1 10669 # number of demand (read+write) hits 52system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits 53system.l2c.overall_hits::0 1294007 # number of overall hits 54system.l2c.overall_hits::1 10669 # number of overall hits 55system.l2c.overall_hits::total 1304676 # number of overall hits 56system.l2c.ReadReq_misses::0 31716 # number of ReadReq misses 57system.l2c.ReadReq_misses::1 27 # number of ReadReq misses 58system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses 59system.l2c.UpgradeReq_misses::0 2911 # number of UpgradeReq misses 60system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses 61system.l2c.ReadExReq_misses::0 141169 # number of ReadExReq misses 62system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses 63system.l2c.demand_misses::0 172885 # number of demand (read+write) misses 64system.l2c.demand_misses::1 27 # number of demand (read+write) misses 65system.l2c.demand_misses::total 172912 # number of demand (read+write) misses 66system.l2c.overall_misses::0 172885 # number of overall misses 67system.l2c.overall_misses::1 27 # number of overall misses 68system.l2c.overall_misses::total 172912 # number of overall misses 69system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 70system.l2c.overall_miss_latency 0 # number of overall miss cycles 71system.l2c.ReadReq_accesses::0 1219932 # number of ReadReq accesses(hits+misses) 72system.l2c.ReadReq_accesses::1 10696 # number of ReadReq accesses(hits+misses) 73system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses) 74system.l2c.Writeback_accesses::0 604613 # number of Writeback accesses(hits+misses) 75system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses) 76system.l2c.UpgradeReq_accesses::0 2937 # number of UpgradeReq accesses(hits+misses) 77system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) 78system.l2c.ReadExReq_accesses::0 246960 # number of ReadExReq accesses(hits+misses) 79system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses) 80system.l2c.demand_accesses::0 1466892 # number of demand (read+write) accesses 81system.l2c.demand_accesses::1 10696 # number of demand (read+write) accesses 82system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses 83system.l2c.overall_accesses::0 1466892 # number of overall (read+write) accesses 84system.l2c.overall_accesses::1 10696 # number of overall (read+write) accesses 85system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses 86system.l2c.ReadReq_miss_rate::0 0.025998 # miss rate for ReadReq accesses 87system.l2c.ReadReq_miss_rate::1 0.002524 # miss rate for ReadReq accesses 88system.l2c.ReadReq_miss_rate::total 0.028522 # miss rate for ReadReq accesses 89system.l2c.UpgradeReq_miss_rate::0 0.991147 # miss rate for UpgradeReq accesses 90system.l2c.ReadExReq_miss_rate::0 0.571627 # miss rate for ReadExReq accesses 91system.l2c.demand_miss_rate::0 0.117858 # miss rate for demand accesses 92system.l2c.demand_miss_rate::1 0.002524 # miss rate for demand accesses 93system.l2c.demand_miss_rate::total 0.120382 # miss rate for demand accesses 94system.l2c.overall_miss_rate::0 0.117858 # miss rate for overall accesses 95system.l2c.overall_miss_rate::1 0.002524 # miss rate for overall accesses 96system.l2c.overall_miss_rate::total 0.120382 # miss rate for overall accesses 97system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 98system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 99system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency 100system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 101system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 102system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency 103system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 104system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 105system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 106system.l2c.blocked::no_targets 0 # number of cycles access was blocked 107system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 108system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 109system.l2c.fast_writes 0 # number of fast writes performed 110system.l2c.cache_copies 0 # number of cache copies performed 111system.l2c.writebacks 102531 # number of writebacks 112system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 113system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 114system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 115system.l2c.overall_mshr_misses 0 # number of overall MSHR misses 116system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 117system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 118system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 119system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 120system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 121system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 122system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses 123system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 124system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 125system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses 126system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 127system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 128system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 129system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 130system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 131system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 132system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 133system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 134system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 135system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 136system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 137system.cf0.dma_write_txs 0 # Number of DMA write transactions. 138system.cpu.dtb.inst_hits 0 # ITB inst hits 139system.cpu.dtb.inst_misses 0 # ITB inst misses 140system.cpu.dtb.read_hits 14940566 # DTB read hits 141system.cpu.dtb.read_misses 7288 # DTB read misses 142system.cpu.dtb.write_hits 11198205 # DTB write hits 143system.cpu.dtb.write_misses 2199 # DTB write misses 144system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 145system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 146system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 147system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 148system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB 149system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 150system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch 151system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 152system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 153system.cpu.dtb.read_accesses 14947854 # DTB read accesses 154system.cpu.dtb.write_accesses 11200404 # DTB write accesses 155system.cpu.dtb.inst_accesses 0 # ITB inst accesses 156system.cpu.dtb.hits 26138771 # DTB hits 157system.cpu.dtb.misses 9487 # DTB misses 158system.cpu.dtb.accesses 26148258 # DTB accesses 159system.cpu.itb.inst_hits 60273889 # ITB inst hits 160system.cpu.itb.inst_misses 4471 # ITB inst misses 161system.cpu.itb.read_hits 0 # DTB read hits 162system.cpu.itb.read_misses 0 # DTB read misses 163system.cpu.itb.write_hits 0 # DTB write hits 164system.cpu.itb.write_misses 0 # DTB write misses 165system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 166system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 167system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 168system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 169system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 170system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 171system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 172system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 173system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 174system.cpu.itb.read_accesses 0 # DTB read accesses 175system.cpu.itb.write_accesses 0 # DTB write accesses 176system.cpu.itb.inst_accesses 60278360 # ITB inst accesses 177system.cpu.itb.hits 60273889 # DTB hits 178system.cpu.itb.misses 4471 # DTB misses 179system.cpu.itb.accesses 60278360 # DTB accesses 180system.cpu.numCycles 4664556206 # number of cpu cycles simulated 181system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 182system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 183system.cpu.num_insts 76532931 # Number of instructions executed 184system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses 185system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 186system.cpu.num_func_calls 1971944 # number of times a function call or return occured 187system.cpu.num_conditional_control_insts 7572657 # number of instructions that are conditional controls 188system.cpu.num_int_insts 68161177 # number of integer instructions 189system.cpu.num_fp_insts 10269 # number of float instructions 190system.cpu.num_int_register_reads 345365607 # number of times the integer registers were read 191system.cpu.num_int_register_writes 72877692 # number of times the integer registers were written 192system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 193system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 194system.cpu.num_mem_refs 27310784 # number of memory refs 195system.cpu.num_load_insts 15607074 # Number of load instructions 196system.cpu.num_store_insts 11703710 # Number of store instructions 197system.cpu.num_idle_cycles 4586920150.977920 # Number of idle cycles 198system.cpu.num_busy_cycles 77636055.022080 # Number of busy cycles 199system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles 200system.cpu.idle_fraction 0.983356 # Percentage of idle cycles 201system.cpu.kern.inst.arm 0 # number of arm instructions executed 202system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed 203system.cpu.icache.replacements 847054 # number of replacements 204system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use 205system.cpu.icache.total_refs 59429083 # Total number of references to valid blocks. 206system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks. 207system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks. 208system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit. 209system.cpu.icache.occ_blocks::0 511.678552 # Average occupied blocks per context 210system.cpu.icache.occ_percent::0 0.999372 # Average percentage of cache occupancy 211system.cpu.icache.ReadReq_hits::0 59429083 # number of ReadReq hits 212system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits 213system.cpu.icache.demand_hits::0 59429083 # number of demand (read+write) hits 214system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 215system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits 216system.cpu.icache.overall_hits::0 59429083 # number of overall hits 217system.cpu.icache.overall_hits::1 0 # number of overall hits 218system.cpu.icache.overall_hits::total 59429083 # number of overall hits 219system.cpu.icache.ReadReq_misses::0 847566 # number of ReadReq misses 220system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses 221system.cpu.icache.demand_misses::0 847566 # number of demand (read+write) misses 222system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 223system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses 224system.cpu.icache.overall_misses::0 847566 # number of overall misses 225system.cpu.icache.overall_misses::1 0 # number of overall misses 226system.cpu.icache.overall_misses::total 847566 # number of overall misses 227system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 228system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 229system.cpu.icache.ReadReq_accesses::0 60276649 # number of ReadReq accesses(hits+misses) 230system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses) 231system.cpu.icache.demand_accesses::0 60276649 # number of demand (read+write) accesses 232system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 233system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses 234system.cpu.icache.overall_accesses::0 60276649 # number of overall (read+write) accesses 235system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 236system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses 237system.cpu.icache.ReadReq_miss_rate::0 0.014061 # miss rate for ReadReq accesses 238system.cpu.icache.demand_miss_rate::0 0.014061 # miss rate for demand accesses 239system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 240system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 241system.cpu.icache.overall_miss_rate::0 0.014061 # miss rate for overall accesses 242system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 243system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 244system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency 245system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 246system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency 247system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency 248system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency 250system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 251system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 252system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 254system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 255system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 256system.cpu.icache.fast_writes 0 # number of fast writes performed 257system.cpu.icache.cache_copies 0 # number of cache copies performed 258system.cpu.icache.writebacks 44721 # number of writebacks 259system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 260system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 261system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 262system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 263system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 264system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 265system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 266system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 267system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 268system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 269system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 270system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 271system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 272system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 273system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 274system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 275system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 276system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 277system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 278system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 279system.cpu.dcache.replacements 622134 # number of replacements 280system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use 281system.cpu.dcache.total_refs 23580069 # Total number of references to valid blocks. 282system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks. 283system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks. 284system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. 285system.cpu.dcache.occ_blocks::0 511.997030 # Average occupied blocks per context 286system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy 287system.cpu.dcache.ReadReq_hits::0 13150366 # number of ReadReq hits 288system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits 289system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits 290system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits 291system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits 292system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits 293system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits 294system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits 295system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits 296system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 297system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits 298system.cpu.dcache.overall_hits::0 23093997 # number of overall hits 299system.cpu.dcache.overall_hits::1 0 # number of overall hits 300system.cpu.dcache.overall_hits::total 23093997 # number of overall hits 301system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses 302system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses 303system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses 304system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses 305system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses 306system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses 307system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses 308system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 309system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses 310system.cpu.dcache.overall_misses::0 614445 # number of overall misses 311system.cpu.dcache.overall_misses::1 0 # number of overall misses 312system.cpu.dcache.overall_misses::total 614445 # number of overall misses 313system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 314system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 315system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses) 316system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses) 317system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses) 318system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses) 319system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses) 320system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses) 321system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses) 322system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses) 323system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses 324system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 325system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses 326system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses 327system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 328system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses 329system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses 330system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses 331system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses 332system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses 333system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 334system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 335system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses 336system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 337system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 338system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 339system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 340system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 341system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 342system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 343system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 344system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 345system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 346system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 347system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 348system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 349system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 350system.cpu.dcache.fast_writes 0 # number of fast writes performed 351system.cpu.dcache.cache_copies 0 # number of cache copies performed 352system.cpu.dcache.writebacks 559892 # number of writebacks 353system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 354system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 355system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 356system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 357system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 358system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 359system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 360system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 361system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 362system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 363system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 364system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 365system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 366system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 367system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 368system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 369system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 370system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 371system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 372system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 373system.iocache.replacements 0 # number of replacements 374system.iocache.tagsinuse 0 # Cycle average of tags in use 375system.iocache.total_refs 0 # Total number of references to valid blocks. 376system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 377system.iocache.avg_refs no_value # Average number of references to valid blocks. 378system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 379system.iocache.demand_hits::0 0 # number of demand (read+write) hits 380system.iocache.demand_hits::1 0 # number of demand (read+write) hits 381system.iocache.demand_hits::total 0 # number of demand (read+write) hits 382system.iocache.overall_hits::0 0 # number of overall hits 383system.iocache.overall_hits::1 0 # number of overall hits 384system.iocache.overall_hits::total 0 # number of overall hits 385system.iocache.demand_misses::0 0 # number of demand (read+write) misses 386system.iocache.demand_misses::1 0 # number of demand (read+write) misses 387system.iocache.demand_misses::total 0 # number of demand (read+write) misses 388system.iocache.overall_misses::0 0 # number of overall misses 389system.iocache.overall_misses::1 0 # number of overall misses 390system.iocache.overall_misses::total 0 # number of overall misses 391system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 392system.iocache.overall_miss_latency 0 # number of overall miss cycles 393system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 394system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses 395system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses 396system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 397system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses 398system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses 399system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 400system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses 401system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 402system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 403system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses 404system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 405system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 406system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency 407system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 408system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 409system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency 410system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 411system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.iocache.blocked::no_targets 0 # number of cycles access was blocked 415system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 416system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 417system.iocache.fast_writes 0 # number of fast writes performed 418system.iocache.cache_copies 0 # number of cache copies performed 419system.iocache.writebacks 0 # number of writebacks 420system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 421system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 422system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 423system.iocache.overall_mshr_misses 0 # number of overall MSHR misses 424system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 425system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 426system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 427system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 428system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 429system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 430system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 431system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 432system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 433system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 434system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 435system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 436system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 437system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 438system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 439system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 440 441---------- End Simulation Statistics ---------- 442