stats.txt revision 9568:cd1351d4d850
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332810 # Number of seconds simulated 4sim_ticks 2332810264000 # Number of ticks simulated 5final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1712706 # Simulator instruction rate (inst/s) 8host_op_rate 2202434 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 66139785958 # Simulator tick rate (ticks/s) 10host_mem_usage 391204 # Number of bytes of host memory used 11host_seconds 35.27 # Real time elapsed on the host 12sim_insts 60408639 # Number of instructions simulated 13sim_ops 77681819 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory 19system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 0 # Total number of read requests seen 53system.physmem.writeReqs 0 # Total number of write requests seen 54system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 0 # Total number of bytes read from memory 56system.physmem.bytesWritten 0 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 59system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 95system.physmem.totGap 0 # Total gap between requests 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 0 # Categorize read packet sizes 99system.physmem.readPktSize::3 0 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes 102system.physmem.readPktSize::6 0 # Categorize read packet sizes 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 0 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes 109system.physmem.writePktSize::6 0 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 142system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 174system.physmem.totQLat 0 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 0 # Sum of mem lat for all requests 176system.physmem.totBusLat 0 # Total cycles spent in databus access 177system.physmem.totBankLat 0 # Total cycles spent in bank access 178system.physmem.avgQLat nan # Average queueing delay per request 179system.physmem.avgBankLat nan # Average bank access latency per request 180system.physmem.avgBusLat nan # Average bus latency per request 181system.physmem.avgMemAccLat nan # Average memory access latency 182system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 0.00 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.00 # Average read queue length over time 189system.physmem.avgWrQLen 0.00 # Average write queue length over time 190system.physmem.readRowHits 0 # Number of row buffer hits during reads 191system.physmem.writeRowHits 0 # Number of row buffer hits during writes 192system.physmem.readRowHitRate nan # Row buffer hit rate for reads 193system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 194system.physmem.avgGap nan # Average gap between requests 195system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 196system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 197system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 198system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 199system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 200system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 201system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) 202system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) 203system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) 204system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) 205system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) 206system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) 207system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 208system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 209system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 210system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 211system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 212system.cf0.dma_write_txs 0 # Number of DMA write transactions. 213system.cpu.dtb.inst_hits 0 # ITB inst hits 214system.cpu.dtb.inst_misses 0 # ITB inst misses 215system.cpu.dtb.read_hits 14971214 # DTB read hits 216system.cpu.dtb.read_misses 7294 # DTB read misses 217system.cpu.dtb.write_hits 11217004 # DTB write hits 218system.cpu.dtb.write_misses 2181 # DTB write misses 219system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 220system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 221system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 222system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 223system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB 224system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 225system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch 226system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 227system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 228system.cpu.dtb.read_accesses 14978508 # DTB read accesses 229system.cpu.dtb.write_accesses 11219185 # DTB write accesses 230system.cpu.dtb.inst_accesses 0 # ITB inst accesses 231system.cpu.dtb.hits 26188218 # DTB hits 232system.cpu.dtb.misses 9475 # DTB misses 233system.cpu.dtb.accesses 26197693 # DTB accesses 234system.cpu.itb.inst_hits 61431840 # ITB inst hits 235system.cpu.itb.inst_misses 4471 # ITB inst misses 236system.cpu.itb.read_hits 0 # DTB read hits 237system.cpu.itb.read_misses 0 # DTB read misses 238system.cpu.itb.write_hits 0 # DTB write hits 239system.cpu.itb.write_misses 0 # DTB write misses 240system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 241system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 242system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 243system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 244system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 245system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 246system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 247system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 248system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 249system.cpu.itb.read_accesses 0 # DTB read accesses 250system.cpu.itb.write_accesses 0 # DTB write accesses 251system.cpu.itb.inst_accesses 61436311 # ITB inst accesses 252system.cpu.itb.hits 61431840 # DTB hits 253system.cpu.itb.misses 4471 # DTB misses 254system.cpu.itb.accesses 61436311 # DTB accesses 255system.cpu.numCycles 4665543516 # number of cpu cycles simulated 256system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 257system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 258system.cpu.committedInsts 60408639 # Number of instructions committed 259system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed 260system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses 261system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 262system.cpu.num_func_calls 2136008 # number of times a function call or return occured 263system.cpu.num_conditional_control_insts 7942113 # number of instructions that are conditional controls 264system.cpu.num_int_insts 68795605 # number of integer instructions 265system.cpu.num_fp_insts 10269 # number of float instructions 266system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read 267system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written 268system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 269system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 270system.cpu.num_mem_refs 27361637 # number of memory refs 271system.cpu.num_load_insts 15639527 # Number of load instructions 272system.cpu.num_store_insts 11722110 # Number of store instructions 273system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles 274system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles 275system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles 276system.cpu.idle_fraction 0.983111 # Percentage of idle cycles 277system.cpu.kern.inst.arm 0 # number of arm instructions executed 278system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed 279system.cpu.icache.replacements 850590 # number of replacements 280system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use 281system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks. 282system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks. 283system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks. 284system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. 285system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor 286system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy 287system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy 288system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits 289system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits 290system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits 291system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits 292system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits 293system.cpu.icache.overall_hits::total 60583498 # number of overall hits 294system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses 295system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses 296system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses 297system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses 298system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses 299system.cpu.icache.overall_misses::total 851102 # number of overall misses 300system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses) 301system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) 302system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses 303system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses 304system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses 305system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses 306system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses 307system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses 308system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses 309system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses 310system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses 311system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses 312system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 313system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 314system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 315system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 316system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 317system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 318system.cpu.icache.fast_writes 0 # number of fast writes performed 319system.cpu.icache.cache_copies 0 # number of cache copies performed 320system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 321system.cpu.l2cache.replacements 62243 # number of replacements 322system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use 323system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks. 324system.cpu.l2cache.sampled_refs 127628 # Sample count of references to valid blocks. 325system.cpu.l2cache.avg_refs 13.084292 # Average number of references to valid blocks. 326system.cpu.l2cache.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. 327system.cpu.l2cache.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor 328system.cpu.l2cache.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor 329system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor 330system.cpu.l2cache.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor 331system.cpu.l2cache.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor 332system.cpu.l2cache.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy 333system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 334system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy 335system.cpu.l2cache.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy 336system.cpu.l2cache.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy 337system.cpu.l2cache.occ_percent::total 0.763050 # Average percentage of cache occupancy 338system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits 339system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits 340system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits 341system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits 342system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits 343system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits 344system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits 345system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 346system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 347system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits 348system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits 349system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits 350system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits 351system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits 352system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits 353system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits 354system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits 355system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits 356system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits 357system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits 358system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits 359system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 360system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 361system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses 362system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses 363system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses 364system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses 365system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses 366system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses 367system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses 368system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 369system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 370system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses 371system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses 372system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses 373system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 374system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 375system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses 376system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses 377system.cpu.l2cache.overall_misses::total 153951 # number of overall misses 378system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) 379system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) 380system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) 381system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) 382system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) 383system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) 384system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) 385system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) 386system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) 387system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) 388system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) 389system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses 390system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses 391system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses 392system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses 393system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses 394system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses 395system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses 396system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses 397system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses 398system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses 399system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses 400system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses 401system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses 402system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses 403system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses 404system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses 405system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses 406system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses 407system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses 408system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses 409system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses 410system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses 411system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses 412system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses 413system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses 414system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses 415system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses 416system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses 417system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses 418system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 419system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 420system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 421system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 422system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 423system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 424system.cpu.l2cache.fast_writes 0 # number of fast writes performed 425system.cpu.l2cache.cache_copies 0 # number of cache copies performed 426system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks 427system.cpu.l2cache.writebacks::total 57863 # number of writebacks 428system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 429system.cpu.dcache.replacements 623337 # number of replacements 430system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use 431system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks. 432system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks. 433system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks. 434system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. 435system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor 436system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 437system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy 438system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits 439system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits 440system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits 441system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits 442system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits 443system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits 444system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits 445system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits 446system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits 447system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits 448system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits 449system.cpu.dcache.overall_hits::total 23142138 # number of overall hits 450system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses 451system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses 452system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses 453system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses 454system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses 455system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses 456system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses 457system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses 458system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses 459system.cpu.dcache.overall_misses::total 615611 # number of overall misses 460system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses) 461system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses) 462system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses) 463system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses) 464system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) 465system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) 466system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) 467system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) 468system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses 469system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses 470system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses 471system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses 472system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses 473system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses 474system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses 475system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses 476system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses 477system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses 478system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses 479system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses 480system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses 481system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses 482system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 483system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 484system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 485system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 486system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 487system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 488system.cpu.dcache.fast_writes 0 # number of fast writes performed 489system.cpu.dcache.cache_copies 0 # number of cache copies performed 490system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks 491system.cpu.dcache.writebacks::total 592643 # number of writebacks 492system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 493system.iocache.replacements 0 # number of replacements 494system.iocache.tagsinuse 0 # Cycle average of tags in use 495system.iocache.total_refs 0 # Total number of references to valid blocks. 496system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 497system.iocache.avg_refs nan # Average number of references to valid blocks. 498system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 499system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 500system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 501system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 502system.iocache.blocked::no_targets 0 # number of cycles access was blocked 503system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 504system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 505system.iocache.fast_writes 0 # number of fast writes performed 506system.iocache.cache_copies 0 # number of cache copies performed 507system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 508 509---------- End Simulation Statistics ---------- 510