stats.txt revision 10038:7eccd14e2610
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332810 # Number of seconds simulated 4sim_ticks 2332810269000 # Number of ticks simulated 5final_tick 2332810269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1274625 # Simulator instruction rate (inst/s) 8host_op_rate 1639090 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49222371545 # Simulator tick rate (ticks/s) 10host_mem_usage 420236 # Number of bytes of host memory used 11host_seconds 47.39 # Real time elapsed on the host 12sim_insts 60408649 # Number of instructions simulated 13sim_ops 77681829 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9071640 # Number of bytes read from this memory 21system.physmem.bytes_read::total 121450656 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141780 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 14118186 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3888717 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 52061952 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 5181500 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 54942190 # Total bandwidth to/from this memory (bytes/s) 54system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 56system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 57system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 58system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 59system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 60system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) 65system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) 66system.membus.throughput 55969605 # Throughput (bytes/s) 67system.membus.data_through_bus 130566470 # Total data (bytes) 68system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 69system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 70system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 71system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 72system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 73system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 74system.cf0.dma_write_txs 0 # Number of DMA write transactions. 75system.iobus.throughput 48895252 # Throughput (bytes/s) 76system.iobus.data_through_bus 114063346 # Total data (bytes) 77system.cpu_clk_domain.clock 500 # Clock period in ticks 78system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 79system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 80system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 81system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 82system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 83system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 84system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 85system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 86system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 87system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 88system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 89system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 90system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 91system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 92system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 93system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 94system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 95system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 96system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 97system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 98system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 99system.cpu.dtb.inst_hits 0 # ITB inst hits 100system.cpu.dtb.inst_misses 0 # ITB inst misses 101system.cpu.dtb.read_hits 14971217 # DTB read hits 102system.cpu.dtb.read_misses 7294 # DTB read misses 103system.cpu.dtb.write_hits 11217004 # DTB write hits 104system.cpu.dtb.write_misses 2181 # DTB write misses 105system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 106system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 108system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 109system.cpu.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB 110system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch 112system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 114system.cpu.dtb.read_accesses 14978511 # DTB read accesses 115system.cpu.dtb.write_accesses 11219185 # DTB write accesses 116system.cpu.dtb.inst_accesses 0 # ITB inst accesses 117system.cpu.dtb.hits 26188221 # DTB hits 118system.cpu.dtb.misses 9475 # DTB misses 119system.cpu.dtb.accesses 26197696 # DTB accesses 120system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 121system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 122system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 123system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 124system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 125system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 126system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 127system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 128system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 129system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 130system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 131system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 132system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 133system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 134system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 135system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 136system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 137system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 138system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 139system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 140system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 141system.cpu.itb.inst_hits 61431840 # ITB inst hits 142system.cpu.itb.inst_misses 4471 # ITB inst misses 143system.cpu.itb.read_hits 0 # DTB read hits 144system.cpu.itb.read_misses 0 # DTB read misses 145system.cpu.itb.write_hits 0 # DTB write hits 146system.cpu.itb.write_misses 0 # DTB write misses 147system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 148system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 149system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 150system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 151system.cpu.itb.flush_entries 2370 # Number of entries that have been flushed from TLB 152system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 153system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 154system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 156system.cpu.itb.read_accesses 0 # DTB read accesses 157system.cpu.itb.write_accesses 0 # DTB write accesses 158system.cpu.itb.inst_accesses 61436311 # ITB inst accesses 159system.cpu.itb.hits 61431840 # DTB hits 160system.cpu.itb.misses 4471 # DTB misses 161system.cpu.itb.accesses 61436311 # DTB accesses 162system.cpu.numCycles 4665620539 # number of cpu cycles simulated 163system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 164system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 165system.cpu.committedInsts 60408649 # Number of instructions committed 166system.cpu.committedOps 77681829 # Number of ops (including micro ops) committed 167system.cpu.num_int_alu_accesses 69130761 # Number of integer alu accesses 168system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 169system.cpu.num_func_calls 2136008 # number of times a function call or return occured 170system.cpu.num_conditional_control_insts 7942115 # number of instructions that are conditional controls 171system.cpu.num_int_insts 69130761 # number of integer instructions 172system.cpu.num_fp_insts 10269 # number of float instructions 173system.cpu.num_int_register_reads 355896757 # number of times the integer registers were read 174system.cpu.num_int_register_writes 74438766 # number of times the integer registers were written 175system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 176system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 177system.cpu.num_mem_refs 27361639 # number of memory refs 178system.cpu.num_load_insts 15639529 # Number of load instructions 179system.cpu.num_store_insts 11722110 # Number of store instructions 180system.cpu.num_idle_cycles 4586822073.007145 # Number of idle cycles 181system.cpu.num_busy_cycles 78798465.992855 # Number of busy cycles 182system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles 183system.cpu.idle_fraction 0.983111 # Percentage of idle cycles 184system.cpu.kern.inst.arm 0 # number of arm instructions executed 185system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed 186system.cpu.icache.tags.replacements 850590 # number of replacements 187system.cpu.icache.tags.tagsinuse 511.678592 # Cycle average of tags in use 188system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. 189system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. 190system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. 191system.cpu.icache.tags.warmup_cycle 5709388000 # Cycle when the warmup percentage was hit. 192system.cpu.icache.tags.occ_blocks::cpu.inst 511.678592 # Average occupied blocks per requestor 193system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy 194system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy 195system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 196system.cpu.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 197system.cpu.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id 198system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id 199system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 200system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 201system.cpu.icache.tags.tag_accesses 62285702 # Number of tag accesses 202system.cpu.icache.tags.data_accesses 62285702 # Number of data accesses 203system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits 204system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits 205system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits 206system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits 207system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits 208system.cpu.icache.overall_hits::total 60583498 # number of overall hits 209system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses 210system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses 211system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses 212system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses 213system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses 214system.cpu.icache.overall_misses::total 851102 # number of overall misses 215system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses) 216system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) 217system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses 218system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses 219system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses 220system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses 221system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses 222system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses 223system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses 224system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses 225system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses 226system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses 227system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 228system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 229system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 230system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 231system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 232system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 233system.cpu.icache.fast_writes 0 # number of fast writes performed 234system.cpu.icache.cache_copies 0 # number of cache copies performed 235system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 236system.cpu.l2cache.tags.replacements 62243 # number of replacements 237system.cpu.l2cache.tags.tagsinuse 50007.272801 # Cycle average of tags in use 238system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. 239system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. 240system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. 241system.cpu.l2cache.tags.warmup_cycle 2316901494000 # Cycle when the warmup percentage was hit. 242system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582911 # Average occupied blocks per requestor 243system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor 244system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor 245system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720467 # Average occupied blocks per requestor 246system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015344 # Average occupied blocks per requestor 247system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy 248system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 249system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy 250system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy 251system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy 252system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy 253system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 254system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id 255system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 256system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 257system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 258system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3589 # Occupied blocks per task id 259system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187 # Occupied blocks per task id 260system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52388 # Occupied blocks per task id 261system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 262system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id 263system.cpu.l2cache.tags.tag_accesses 17035899 # Number of tag accesses 264system.cpu.l2cache.tags.data_accesses 17035899 # Number of data accesses 265system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits 266system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits 267system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits 268system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits 269system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits 270system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits 271system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits 272system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 273system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 274system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits 275system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits 276system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits 277system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits 278system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits 279system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits 280system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits 281system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits 282system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits 283system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits 284system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits 285system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits 286system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 287system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 288system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses 289system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses 290system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses 291system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses 292system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses 293system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses 294system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses 295system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 296system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 297system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses 298system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses 299system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses 300system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 301system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 302system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses 303system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses 304system.cpu.l2cache.overall_misses::total 153951 # number of overall misses 305system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) 306system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) 307system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) 308system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) 309system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) 310system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) 311system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) 312system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) 313system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) 314system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) 315system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) 316system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses 317system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses 318system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses 319system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses 320system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses 321system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses 322system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses 323system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses 324system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses 325system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses 326system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses 327system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses 328system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses 329system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses 330system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses 331system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses 332system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses 333system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses 334system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses 335system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses 336system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses 337system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses 338system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses 339system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses 340system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses 341system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses 342system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses 343system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses 344system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses 345system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 346system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 347system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 348system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 349system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 350system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 351system.cpu.l2cache.fast_writes 0 # number of fast writes performed 352system.cpu.l2cache.cache_copies 0 # number of cache copies performed 353system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks 354system.cpu.l2cache.writebacks::total 57863 # number of writebacks 355system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 356system.cpu.dcache.tags.replacements 623337 # number of replacements 357system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use 358system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. 359system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. 360system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. 361system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. 362system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor 363system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 364system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 365system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 366system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id 367system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 368system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 369system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 370system.cpu.dcache.tags.tag_accesses 97632617 # Number of tag accesses 371system.cpu.dcache.tags.data_accesses 97632617 # Number of data accesses 372system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits 373system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits 374system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits 375system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits 376system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits 377system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits 378system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits 379system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits 380system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits 381system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits 382system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits 383system.cpu.dcache.overall_hits::total 23142138 # number of overall hits 384system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses 385system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses 386system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses 387system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses 388system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses 389system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses 390system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses 391system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses 392system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses 393system.cpu.dcache.overall_misses::total 615611 # number of overall misses 394system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses) 395system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses) 396system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses) 397system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) 399system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) 400system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) 401system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) 402system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses 403system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses 404system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses 405system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses 406system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses 407system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses 408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses 409system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses 410system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses 411system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses 412system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses 413system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses 414system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses 415system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses 416system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 419system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 421system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 422system.cpu.dcache.fast_writes 0 # number of fast writes performed 423system.cpu.dcache.cache_copies 0 # number of cache copies performed 424system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks 425system.cpu.dcache.writebacks::total 592643 # number of writebacks 426system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 427system.cpu.toL2Bus.throughput 59102669 # Throughput (bytes/s) 428system.cpu.toL2Bus.data_through_bus 137875314 # Total data (bytes) 429system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 430system.iocache.tags.replacements 0 # number of replacements 431system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 432system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 433system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 434system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 435system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 436system.iocache.tags.tag_accesses 0 # Number of tag accesses 437system.iocache.tags.data_accesses 0 # Number of data accesses 438system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 439system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 440system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 441system.iocache.blocked::no_targets 0 # number of cycles access was blocked 442system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 443system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 444system.iocache.fast_writes 0 # number of fast writes performed 445system.iocache.cache_copies 0 # number of cache copies performed 446system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 447 448---------- End Simulation Statistics ---------- 449