stats.txt revision 9005:f681719e2e99
16145Snate@binkert.org 26145Snate@binkert.org---------- Begin Simulation Statistics ---------- 36145Snate@binkert.orgsim_seconds 2.332330 # Number of seconds simulated 46145Snate@binkert.orgsim_ticks 2332330037000 # Number of ticks simulated 56145Snate@binkert.orgfinal_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 66145Snate@binkert.orgsim_freq 1000000000000 # Frequency of simulated ticks 76145Snate@binkert.orghost_inst_rate 1538399 # Simulator instruction rate (inst/s) 86145Snate@binkert.orghost_op_rate 1985816 # Simulator op (including micro ops) rate (op/s) 96145Snate@binkert.orghost_tick_rate 60412799239 # Simulator tick rate (ticks/s) 106145Snate@binkert.orghost_mem_usage 379756 # Number of bytes of host memory used 116145Snate@binkert.orghost_seconds 38.61 # Real time elapsed on the host 126145Snate@binkert.orgsim_insts 59392246 # Number of instructions simulated 136145Snate@binkert.orgsim_ops 76665494 # Number of ops (including micro ops) simulated 146145Snate@binkert.orgsystem.physmem.bytes_read 122661296 # Number of bytes read from this memory 156145Snate@binkert.orgsystem.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory 166145Snate@binkert.orgsystem.physmem.bytes_written 9590216 # Number of bytes written to this memory 176145Snate@binkert.orgsystem.physmem.num_reads 14137091 # Number of read requests responded to by this memory 186145Snate@binkert.orgsystem.physmem.num_writes 856679 # Number of write requests responded to by this memory 196145Snate@binkert.orgsystem.physmem.num_other 0 # Number of other requests responded to by this memory 206145Snate@binkert.orgsystem.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s) 216145Snate@binkert.orgsystem.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s) 226145Snate@binkert.orgsystem.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s) 236145Snate@binkert.orgsystem.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s) 246145Snate@binkert.orgsystem.realview.nvmem.bytes_read 20 # Number of bytes read from this memory 256145Snate@binkert.orgsystem.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory 266145Snate@binkert.orgsystem.realview.nvmem.bytes_written 0 # Number of bytes written to this memory 276145Snate@binkert.orgsystem.realview.nvmem.num_reads 5 # Number of read requests responded to by this memory 286145Snate@binkert.orgsystem.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory 296145Snate@binkert.orgsystem.realview.nvmem.num_other 0 # Number of other requests responded to by this memory 306145Snate@binkert.orgsystem.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) 316145Snate@binkert.orgsystem.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) 326145Snate@binkert.orgsystem.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) 336145Snate@binkert.orgsystem.l2c.replacements 117012 # number of replacements 346145Snate@binkert.orgsystem.l2c.tagsinuse 24288.656748 # Cycle average of tags in use 356145Snate@binkert.orgsystem.l2c.total_refs 1527554 # Total number of references to valid blocks. 366145Snate@binkert.orgsystem.l2c.sampled_refs 146810 # Sample count of references to valid blocks. 376145Snate@binkert.orgsystem.l2c.avg_refs 10.404972 # Average number of references to valid blocks. 386145Snate@binkert.orgsystem.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 396145Snate@binkert.orgsystem.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor 406154Snate@binkert.orgsystem.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor 416154Snate@binkert.orgsystem.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor 426154Snate@binkert.orgsystem.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor 436145Snate@binkert.orgsystem.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor 446145Snate@binkert.orgsystem.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy 456145Snate@binkert.orgsystem.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy 466145Snate@binkert.orgsystem.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy 476145Snate@binkert.orgsystem.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy 486145Snate@binkert.orgsystem.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy 496145Snate@binkert.orgsystem.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy 506145Snate@binkert.orgsystem.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits 516145Snate@binkert.orgsystem.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits 526145Snate@binkert.orgsystem.l2c.ReadReq_hits::cpu.inst 835264 # number of ReadReq hits 536145Snate@binkert.orgsystem.l2c.ReadReq_hits::cpu.data 357385 # number of ReadReq hits 546145Snate@binkert.orgsystem.l2c.ReadReq_hits::total 1203303 # number of ReadReq hits 556145Snate@binkert.orgsystem.l2c.Writeback_hits::writebacks 605735 # number of Writeback hits 566145Snate@binkert.orgsystem.l2c.Writeback_hits::total 605735 # number of Writeback hits 576145Snate@binkert.orgsystem.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 586145Snate@binkert.orgsystem.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits 596145Snate@binkert.orgsystem.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits 606145Snate@binkert.orgsystem.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits 616145Snate@binkert.orgsystem.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits 626145Snate@binkert.orgsystem.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits 636145Snate@binkert.orgsystem.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits 646145Snate@binkert.orgsystem.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits 656145Snate@binkert.orgsystem.l2c.demand_hits::total 1309459 # number of demand (read+write) hits 666145Snate@binkert.orgsystem.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits 676145Snate@binkert.orgsystem.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits 686145Snate@binkert.orgsystem.l2c.overall_hits::cpu.inst 835264 # number of overall hits 696145Snate@binkert.orgsystem.l2c.overall_hits::cpu.data 463541 # number of overall hits 706145Snate@binkert.orgsystem.l2c.overall_hits::total 1309459 # number of overall hits 716145Snate@binkert.orgsystem.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses 726145Snate@binkert.orgsystem.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses 736145Snate@binkert.orgsystem.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses 746145Snate@binkert.orgsystem.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses 756145Snate@binkert.orgsystem.l2c.ReadReq_misses::total 31808 # number of ReadReq misses 766145Snate@binkert.orgsystem.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses 776145Snate@binkert.orgsystem.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses 786145Snate@binkert.orgsystem.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses 796145Snate@binkert.orgsystem.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses 806145Snate@binkert.orgsystem.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses 816145Snate@binkert.orgsystem.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses 82system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses 83system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses 84system.l2c.demand_misses::total 172858 # number of demand (read+write) misses 85system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses 86system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses 87system.l2c.overall_misses::cpu.inst 14304 # number of overall misses 88system.l2c.overall_misses::cpu.data 158515 # number of overall misses 89system.l2c.overall_misses::total 172858 # number of overall misses 90system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses) 91system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) 92system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses) 93system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses) 94system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses) 95system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses) 96system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses) 97system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses) 98system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) 99system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses) 100system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses) 101system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses 102system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses 103system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses 104system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses 105system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses 106system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses 107system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses 108system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses 109system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses 110system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses 111system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses 112system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses 113system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses 114system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses 115system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses 116system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses 117system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses 118system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses 119system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses 120system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses 121system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses 122system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses 123system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses 124system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses 125system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 126system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 127system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 128system.l2c.blocked::no_targets 0 # number of cycles access was blocked 129system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 130system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 131system.l2c.fast_writes 0 # number of fast writes performed 132system.l2c.cache_copies 0 # number of cache copies performed 133system.l2c.writebacks::writebacks 102725 # number of writebacks 134system.l2c.writebacks::total 102725 # number of writebacks 135system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 136system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 137system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 138system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 139system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 140system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 141system.cf0.dma_write_txs 0 # Number of DMA write transactions. 142system.cpu.dtb.inst_hits 0 # ITB inst hits 143system.cpu.dtb.inst_misses 0 # ITB inst misses 144system.cpu.dtb.read_hits 14971229 # DTB read hits 145system.cpu.dtb.read_misses 7293 # DTB read misses 146system.cpu.dtb.write_hits 11217018 # DTB write hits 147system.cpu.dtb.write_misses 2181 # DTB write misses 148system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 149system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 151system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 152system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB 153system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 154system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch 155system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 156system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 157system.cpu.dtb.read_accesses 14978522 # DTB read accesses 158system.cpu.dtb.write_accesses 11219199 # DTB write accesses 159system.cpu.dtb.inst_accesses 0 # ITB inst accesses 160system.cpu.dtb.hits 26188247 # DTB hits 161system.cpu.dtb.misses 9474 # DTB misses 162system.cpu.dtb.accesses 26197721 # DTB accesses 163system.cpu.itb.inst_hits 60403303 # ITB inst hits 164system.cpu.itb.inst_misses 4471 # ITB inst misses 165system.cpu.itb.read_hits 0 # DTB read hits 166system.cpu.itb.read_misses 0 # DTB read misses 167system.cpu.itb.write_hits 0 # DTB write hits 168system.cpu.itb.write_misses 0 # DTB write misses 169system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 170system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 171system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 172system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 173system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 174system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 175system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 176system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 177system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 178system.cpu.itb.read_accesses 0 # DTB read accesses 179system.cpu.itb.write_accesses 0 # DTB write accesses 180system.cpu.itb.inst_accesses 60407774 # ITB inst accesses 181system.cpu.itb.hits 60403303 # DTB hits 182system.cpu.itb.misses 4471 # DTB misses 183system.cpu.itb.accesses 60407774 # DTB accesses 184system.cpu.numCycles 4664583062 # number of cpu cycles simulated 185system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 186system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 187system.cpu.committedInsts 59392246 # Number of instructions committed 188system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed 189system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses 190system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 191system.cpu.num_func_calls 1972385 # number of times a function call or return occured 192system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls 193system.cpu.num_int_insts 68281415 # number of integer instructions 194system.cpu.num_fp_insts 10269 # number of float instructions 195system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read 196system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written 197system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 198system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 199system.cpu.num_mem_refs 27361692 # number of memory refs 200system.cpu.num_load_insts 15639569 # Number of load instructions 201system.cpu.num_store_insts 11722123 # Number of store instructions 202system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles 203system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles 204system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles 205system.cpu.idle_fraction 0.983328 # Percentage of idle cycles 206system.cpu.kern.inst.arm 0 # number of arm instructions executed 207system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed 208system.cpu.icache.replacements 850612 # number of replacements 209system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use 210system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks. 211system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks. 212system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks. 213system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit. 214system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor 215system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy 216system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy 217system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits 218system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits 219system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits 220system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits 221system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits 222system.cpu.icache.overall_hits::total 59554939 # number of overall hits 223system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses 224system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses 225system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses 226system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses 227system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses 228system.cpu.icache.overall_misses::total 851124 # number of overall misses 229system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses) 230system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses) 231system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses 232system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses 233system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses 234system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses 235system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses 236system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses 237system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses 238system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 239system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 240system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 241system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 242system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 243system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 244system.cpu.icache.fast_writes 0 # number of fast writes performed 245system.cpu.icache.cache_copies 0 # number of cache copies performed 246system.cpu.icache.writebacks::writebacks 44595 # number of writebacks 247system.cpu.icache.writebacks::total 44595 # number of writebacks 248system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 249system.cpu.dcache.replacements 623347 # number of replacements 250system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use 251system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks. 252system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks. 253system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks. 254system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. 255system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor 256system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 257system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy 258system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits 259system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits 260system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits 261system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits 262system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits 263system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits 264system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits 265system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits 266system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits 267system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits 268system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits 269system.cpu.dcache.overall_hits::total 23142161 # number of overall hits 270system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses 271system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses 272system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses 273system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses 274system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses 275system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses 276system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses 277system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses 278system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses 279system.cpu.dcache.overall_misses::total 615615 # number of overall misses 280system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses) 281system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses) 282system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses) 283system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses) 284system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses) 285system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses) 286system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses) 287system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses) 288system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses 289system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses 290system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses 291system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses 292system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses 293system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses 294system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses 295system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses 296system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses 297system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 298system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 299system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 300system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 301system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 302system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 303system.cpu.dcache.fast_writes 0 # number of fast writes performed 304system.cpu.dcache.cache_copies 0 # number of cache copies performed 305system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks 306system.cpu.dcache.writebacks::total 561140 # number of writebacks 307system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 308system.iocache.replacements 0 # number of replacements 309system.iocache.tagsinuse 0 # Cycle average of tags in use 310system.iocache.total_refs 0 # Total number of references to valid blocks. 311system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 312system.iocache.avg_refs nan # Average number of references to valid blocks. 313system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 314system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 315system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 316system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 317system.iocache.blocked::no_targets 0 # number of cycles access was blocked 318system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 319system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 320system.iocache.fast_writes 0 # number of fast writes performed 321system.iocache.cache_copies 0 # number of cache copies performed 322system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 323 324---------- End Simulation Statistics ---------- 325