stats.txt revision 10036:80e84beef3bb
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.332810 # Number of seconds simulated 4sim_ticks 2332810264000 # Number of ticks simulated 5final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1656319 # Simulator instruction rate (inst/s) 8host_op_rate 2129924 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63962280307 # Simulator tick rate (ticks/s) 10host_mem_usage 398176 # Number of bytes of host memory used 11host_seconds 36.47 # Real time elapsed on the host 12sim_insts 60408639 # Number of instructions simulated 13sim_ops 77681819 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory 21system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory 26system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory 27system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory 36system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) 54system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 55system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 56system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 57system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 58system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 59system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 60system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) 61system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) 62system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) 63system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) 65system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) 66system.membus.throughput 55969585 # Throughput (bytes/s) 67system.membus.data_through_bus 130566422 # Total data (bytes) 68system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 69system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 70system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 71system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 72system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 73system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 74system.cf0.dma_write_txs 0 # Number of DMA write transactions. 75system.iobus.throughput 48895252 # Throughput (bytes/s) 76system.iobus.data_through_bus 114063346 # Total data (bytes) 77system.cpu_clk_domain.clock 500 # Clock period in ticks 78system.cpu.dtb.inst_hits 0 # ITB inst hits 79system.cpu.dtb.inst_misses 0 # ITB inst misses 80system.cpu.dtb.read_hits 14971214 # DTB read hits 81system.cpu.dtb.read_misses 7294 # DTB read misses 82system.cpu.dtb.write_hits 11217004 # DTB write hits 83system.cpu.dtb.write_misses 2181 # DTB write misses 84system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 85system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 86system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 87system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 88system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB 89system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 90system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch 91system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 92system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions 93system.cpu.dtb.read_accesses 14978508 # DTB read accesses 94system.cpu.dtb.write_accesses 11219185 # DTB write accesses 95system.cpu.dtb.inst_accesses 0 # ITB inst accesses 96system.cpu.dtb.hits 26188218 # DTB hits 97system.cpu.dtb.misses 9475 # DTB misses 98system.cpu.dtb.accesses 26197693 # DTB accesses 99system.cpu.itb.inst_hits 61431840 # ITB inst hits 100system.cpu.itb.inst_misses 4471 # ITB inst misses 101system.cpu.itb.read_hits 0 # DTB read hits 102system.cpu.itb.read_misses 0 # DTB read misses 103system.cpu.itb.write_hits 0 # DTB write hits 104system.cpu.itb.write_misses 0 # DTB write misses 105system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 106system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 108system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 109system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 110system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 112system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.itb.read_accesses 0 # DTB read accesses 115system.cpu.itb.write_accesses 0 # DTB write accesses 116system.cpu.itb.inst_accesses 61436311 # ITB inst accesses 117system.cpu.itb.hits 61431840 # DTB hits 118system.cpu.itb.misses 4471 # DTB misses 119system.cpu.itb.accesses 61436311 # DTB accesses 120system.cpu.numCycles 4665620529 # number of cpu cycles simulated 121system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 122system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 123system.cpu.committedInsts 60408639 # Number of instructions committed 124system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed 125system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses 126system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses 127system.cpu.num_func_calls 2136008 # number of times a function call or return occured 128system.cpu.num_conditional_control_insts 7942113 # number of instructions that are conditional controls 129system.cpu.num_int_insts 68795605 # number of integer instructions 130system.cpu.num_fp_insts 10269 # number of float instructions 131system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read 132system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written 133system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 134system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written 135system.cpu.num_mem_refs 27361637 # number of memory refs 136system.cpu.num_load_insts 15639527 # Number of load instructions 137system.cpu.num_store_insts 11722110 # Number of store instructions 138system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles 139system.cpu.num_busy_cycles 78798455.992855 # Number of busy cycles 140system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles 141system.cpu.idle_fraction 0.983111 # Percentage of idle cycles 142system.cpu.kern.inst.arm 0 # number of arm instructions executed 143system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed 144system.cpu.icache.tags.replacements 850590 # number of replacements 145system.cpu.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use 146system.cpu.icache.tags.total_refs 60583498 # Total number of references to valid blocks. 147system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. 148system.cpu.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. 149system.cpu.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. 150system.cpu.icache.tags.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor 151system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy 152system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy 153system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 154system.cpu.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 155system.cpu.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id 156system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id 157system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 158system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 159system.cpu.icache.tags.tag_accesses 62285702 # Number of tag accesses 160system.cpu.icache.tags.data_accesses 62285702 # Number of data accesses 161system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits 162system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits 163system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits 164system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits 165system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits 166system.cpu.icache.overall_hits::total 60583498 # number of overall hits 167system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses 168system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses 169system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses 170system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses 171system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses 172system.cpu.icache.overall_misses::total 851102 # number of overall misses 173system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses) 174system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) 175system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses 176system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses 177system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses 178system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses 179system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses 180system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses 181system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses 182system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses 183system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses 184system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses 185system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 186system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 187system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 188system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 189system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 190system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 191system.cpu.icache.fast_writes 0 # number of fast writes performed 192system.cpu.icache.cache_copies 0 # number of cache copies performed 193system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 194system.cpu.l2cache.tags.replacements 62243 # number of replacements 195system.cpu.l2cache.tags.tagsinuse 50007.272909 # Cycle average of tags in use 196system.cpu.l2cache.tags.total_refs 1669922 # Total number of references to valid blocks. 197system.cpu.l2cache.tags.sampled_refs 127628 # Sample count of references to valid blocks. 198system.cpu.l2cache.tags.avg_refs 13.084292 # Average number of references to valid blocks. 199system.cpu.l2cache.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. 200system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor 201system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor 202system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor 203system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor 204system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor 205system.cpu.l2cache.tags.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy 206system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 207system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy 208system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy 209system.cpu.l2cache.tags.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy 210system.cpu.l2cache.tags.occ_percent::total 0.763050 # Average percentage of cache occupancy 211system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 212system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id 213system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 214system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 215system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 216system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3589 # Occupied blocks per task id 217system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187 # Occupied blocks per task id 218system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52388 # Occupied blocks per task id 219system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 220system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id 221system.cpu.l2cache.tags.tag_accesses 17035899 # Number of tag accesses 222system.cpu.l2cache.tags.data_accesses 17035899 # Number of data accesses 223system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits 224system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits 225system.cpu.l2cache.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits 226system.cpu.l2cache.ReadReq_hits::cpu.data 366771 # number of ReadReq hits 227system.cpu.l2cache.ReadReq_hits::total 1216278 # number of ReadReq hits 228system.cpu.l2cache.Writeback_hits::writebacks 592643 # number of Writeback hits 229system.cpu.l2cache.Writeback_hits::total 592643 # number of Writeback hits 230system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 231system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 232system.cpu.l2cache.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits 233system.cpu.l2cache.ReadExReq_hits::total 113739 # number of ReadExReq hits 234system.cpu.l2cache.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits 235system.cpu.l2cache.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits 236system.cpu.l2cache.demand_hits::cpu.inst 838871 # number of demand (read+write) hits 237system.cpu.l2cache.demand_hits::cpu.data 480510 # number of demand (read+write) hits 238system.cpu.l2cache.demand_hits::total 1330017 # number of demand (read+write) hits 239system.cpu.l2cache.overall_hits::cpu.dtb.walker 7507 # number of overall hits 240system.cpu.l2cache.overall_hits::cpu.itb.walker 3129 # number of overall hits 241system.cpu.l2cache.overall_hits::cpu.inst 838871 # number of overall hits 242system.cpu.l2cache.overall_hits::cpu.data 480510 # number of overall hits 243system.cpu.l2cache.overall_hits::total 1330017 # number of overall hits 244system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 245system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses 246system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses 247system.cpu.l2cache.ReadReq_misses::cpu.data 9871 # number of ReadReq misses 248system.cpu.l2cache.ReadReq_misses::total 20483 # number of ReadReq misses 249system.cpu.l2cache.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses 250system.cpu.l2cache.UpgradeReq_misses::total 2919 # number of UpgradeReq misses 251system.cpu.l2cache.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses 252system.cpu.l2cache.ReadExReq_misses::total 133468 # number of ReadExReq misses 253system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 254system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses 255system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses 256system.cpu.l2cache.demand_misses::cpu.data 143339 # number of demand (read+write) misses 257system.cpu.l2cache.demand_misses::total 153951 # number of demand (read+write) misses 258system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 259system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses 260system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses 261system.cpu.l2cache.overall_misses::cpu.data 143339 # number of overall misses 262system.cpu.l2cache.overall_misses::total 153951 # number of overall misses 263system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) 264system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) 265system.cpu.l2cache.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) 266system.cpu.l2cache.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) 267system.cpu.l2cache.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) 268system.cpu.l2cache.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) 269system.cpu.l2cache.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) 270system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) 271system.cpu.l2cache.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) 272system.cpu.l2cache.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) 273system.cpu.l2cache.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) 274system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses 275system.cpu.l2cache.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses 276system.cpu.l2cache.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses 277system.cpu.l2cache.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses 278system.cpu.l2cache.demand_accesses::total 1483968 # number of demand (read+write) accesses 279system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses 280system.cpu.l2cache.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses 281system.cpu.l2cache.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses 282system.cpu.l2cache.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses 283system.cpu.l2cache.overall_accesses::total 1483968 # number of overall (read+write) accesses 284system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses 285system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses 286system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses 287system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses 288system.cpu.l2cache.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses 289system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses 290system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses 291system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses 292system.cpu.l2cache.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses 293system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses 294system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses 295system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses 296system.cpu.l2cache.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses 297system.cpu.l2cache.demand_miss_rate::total 0.103743 # miss rate for demand accesses 298system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses 299system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses 300system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses 301system.cpu.l2cache.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses 302system.cpu.l2cache.overall_miss_rate::total 0.103743 # miss rate for overall accesses 303system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 304system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 305system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 306system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 307system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 308system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 309system.cpu.l2cache.fast_writes 0 # number of fast writes performed 310system.cpu.l2cache.cache_copies 0 # number of cache copies performed 311system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks 312system.cpu.l2cache.writebacks::total 57863 # number of writebacks 313system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 314system.cpu.dcache.tags.replacements 623337 # number of replacements 315system.cpu.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use 316system.cpu.dcache.tags.total_refs 23628343 # Total number of references to valid blocks. 317system.cpu.dcache.tags.sampled_refs 623849 # Sample count of references to valid blocks. 318system.cpu.dcache.tags.avg_refs 37.875100 # Average number of references to valid blocks. 319system.cpu.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. 320system.cpu.dcache.tags.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor 321system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 322system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 323system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 324system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id 325system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 326system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id 327system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 328system.cpu.dcache.tags.tag_accesses 97632617 # Number of tag accesses 329system.cpu.dcache.tags.data_accesses 97632617 # Number of data accesses 330system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits 331system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits 332system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits 333system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits 334system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits 335system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits 336system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits 337system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits 338system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits 339system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits 340system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits 341system.cpu.dcache.overall_hits::total 23142138 # number of overall hits 342system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses 343system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses 344system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses 345system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses 346system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses 347system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses 348system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses 349system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses 350system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses 351system.cpu.dcache.overall_misses::total 615611 # number of overall misses 352system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses) 353system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses) 354system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses) 355system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses) 356system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) 357system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) 358system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) 359system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) 360system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses 361system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses 362system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses 363system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses 364system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses 365system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses 366system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses 367system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses 368system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses 369system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses 370system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses 371system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses 372system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses 373system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses 374system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 377system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 378system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.cpu.dcache.fast_writes 0 # number of fast writes performed 381system.cpu.dcache.cache_copies 0 # number of cache copies performed 382system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks 383system.cpu.dcache.writebacks::total 592643 # number of writebacks 384system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 385system.cpu.toL2Bus.throughput 59102649 # Throughput (bytes/s) 386system.cpu.toL2Bus.data_through_bus 137875266 # Total data (bytes) 387system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 388system.iocache.tags.replacements 0 # number of replacements 389system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 390system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 391system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 392system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 393system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 394system.iocache.tags.tag_accesses 0 # Number of tag accesses 395system.iocache.tags.data_accesses 0 # Number of data accesses 396system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.iocache.blocked::no_targets 0 # number of cycles access was blocked 400system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.iocache.fast_writes 0 # number of fast writes performed 403system.iocache.cache_copies 0 # number of cache copies performed 404system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 405 406---------- End Simulation Statistics ---------- 407