/gem5/src/cpu/minor/ |
H A D | dyn_inst.cc | 94 assert(staticInst); 95 return !(staticInst->isMicroop() && !staticInst->isLastMicroop()); 101 return isInst() && staticInst->opClass() == No_OpClass; 127 else if (inst.staticInst) 128 os << inst.staticInst->getName(); 189 unsigned int num_src_regs = staticInst->numSrcRegs(); 190 unsigned int num_dest_regs = staticInst->numDestRegs(); 196 if (!staticInst->isMacroop()) { 201 printRegName(regs_str, staticInst [all...] |
H A D | scoreboard.cc | 116 StaticInstPtr staticInst = inst->staticInst; 117 unsigned int num_dests = staticInst->numDestRegs(); 124 staticInst->destRegIdx(dest_index), thread_context); 162 StaticInstPtr staticInst = inst->staticInst; 163 unsigned int num_srcs = staticInst->numSrcRegs(); 166 RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index), 188 StaticInstPtr staticInst = inst->staticInst; [all...] |
H A D | dyn_inst.hh | 165 StaticInstPtr staticInst; member in class:Minor::MinorDynInst 236 staticInst(NULL), id(id_), traceData(NULL), 259 bool isMemRef() const { return isInst() && staticInst->isMemRef(); }
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H A D | execute.cc | 227 (inst->staticInst->isSerializeAfter() || 228 inst->staticInst->isSquashAfter() || 229 inst->staticInst->isIprAccess()); 244 TheISA::advancePC(target, inst->staticInst); 331 bool is_load = inst->staticInst->isLoad(); 332 bool is_store = inst->staticInst->isStore(); 333 bool is_atomic = inst->staticInst->isAtomic(); 334 bool is_prefetch = inst->staticInst->isDataPrefetch(); 345 if (inst->staticInst->isPrefetch()) { 354 fault->invoke(thread, inst->staticInst); [all...] |
/gem5/src/cpu/ |
H A D | inteltrace.cc | 53 if (staticInst->isLoad()) { 55 } else if (staticInst->isStore()) {
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H A D | nativetrace.cc | 63 if (!staticInst->isMicroop() || staticInst->isLastMicroop())
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H A D | base_dyn_inst.hh | 154 const StaticInstPtr staticInst; member in class:BaseDynInst 414 * @param staticInst A StaticInstPtr to the underlying instruction. 420 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop, 427 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop); 500 TheISA::advancePC(tempPC, staticInst); 507 bool isNop() const { return staticInst->isNop(); } 508 bool isMemRef() const { return staticInst->isMemRef(); } 509 bool isLoad() const { return staticInst->isLoad(); } 510 bool isStore() const { return staticInst->isStore(); } 511 bool isAtomic() const { return staticInst [all...] |
H A D | inteltrace.hh | 68 const StaticInstPtr staticInst, TheISA::PCState pc, 74 return new IntelTraceRecord(when, tc, staticInst, pc, macroStaticInst); 67 getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, TheISA::PCState pc, const StaticInstPtr macroStaticInst = NULL) argument
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H A D | exetrace.hh | 72 const StaticInstPtr staticInst, TheISA::PCState pc, 79 staticInst, pc, macroStaticInst); 71 getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, TheISA::PCState pc, const StaticInstPtr macroStaticInst = NULL) argument
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H A D | inst_pb_trace.cc | 61 if ((macroStaticInst && staticInst->isFirstMicroop()) || 62 !staticInst->isMicroop()) { 63 tracer.traceInst(thread, staticInst, pc); 68 tracer.traceMem(staticInst, getAddr(), getSize(), getFlags());
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H A D | nativetrace.hh | 82 const StaticInstPtr staticInst, TheISA::PCState pc, 86 staticInst, pc, macroStaticInst); 81 getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, TheISA::PCState pc, const StaticInstPtr macroStaticInst = NULL) argument
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H A D | exetrace.cc | 200 if (Debug::ExecMacro && staticInst->isMicroop() && 202 macroStaticInst && staticInst->isFirstMicroop()) || 204 macroStaticInst && staticInst->isLastMicroop()))) { 207 if (Debug::ExecMicro || !staticInst->isMicroop()) { 208 traceInst(staticInst, true);
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H A D | base_dyn_inst_impl.hh | 66 : staticInst(_staticInst), cpu(cpu), 85 : staticInst(_staticInst), traceData(NULL), macroop(_macroop) 189 std::cout << staticInst->disassemble(pc.instAddr()); 199 << staticInst->disassemble(pc.instAddr());
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/gem5/src/arch/arm/tracers/ |
H A D | tarmac_tracer.hh | 67 : thread(_thread), staticInst(_staticInst), pc(_pc) 74 const StaticInstPtr staticInst; member in class:Trace::TarmacContext 101 const StaticInstPtr staticInst,
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H A D | tarmac_tracer.cc | 77 const StaticInstPtr staticInst, 88 return new TarmacTracerRecordV8(when, tc, staticInst, pc, *this, 92 return new TarmacTracerRecord(when, tc, staticInst, pc, *this, 76 getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, ArmISA::PCState pc, const StaticInstPtr macroStaticInst) argument
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H A D | tarmac_base.cc | 65 const StaticInstPtr staticInst, 69 opcode(staticInst->machInst & 0xffffffff), 70 disassemble(staticInst->disassemble(addr)), 62 InstEntry( ThreadContext* thread, PCState pc, const StaticInstPtr staticInst, bool predicate) argument
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H A D | tarmac_record.cc | 121 : InstEntry(tarmCtx.thread, tarmCtx.pc, tarmCtx.staticInst, predicate) 126 tarmCtx.staticInst.get() 147 loadAccess(tarmCtx.staticInst->isLoad()) 314 for (auto reg = 0; reg < staticInst->numDestRegs(); ++reg) { 316 RegId reg_id = staticInst->destRegIdx(reg); 344 staticInst->isMicroop()? macroStaticInst : staticInst, 348 if (!staticInst->isMicroop()) { 367 if (staticInst->isFirstMicroop()) { 374 if (staticInst [all...] |
H A D | tarmac_record_v8.cc | 105 tarmCtx.staticInst.get() 161 for (auto reg = 0; reg < staticInst->numDestRegs(); ++reg) { 163 RegId reg_id = staticInst->destRegIdx(reg);
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H A D | tarmac_parser.hh | 243 getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst, argument 251 return new TarmacParserRecord(when, tc, staticInst, pc, *this,
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H A D | tarmac_base.hh | 89 const StaticInstPtr staticInst,
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H A D | tarmac_parser.cc | 745 TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst, argument 752 << ", opcode: 0x" << hex << (staticInst->machInst & 0xffffffff) 754 << ", disasm: " << staticInst->disassemble(pc.pc()) << "]" 784 if (!staticInst->isMicroop() || staticInst->isLastMicroop()) { 786 if (parent.macroopInProgress && !staticInst->isLastMicroop()) { 795 staticInst.get() 805 printMismatchHeader(staticInst, pc); 814 printMismatchHeader(staticInst, pc); 828 printMismatchHeader(staticInst, p [all...] |
/gem5/src/cpu/o3/probe/ |
H A D | simple_trace.cc | 49 dynInst->staticInst->disassemble(dynInst->instAddr())); 56 dynInst->staticInst->disassemble(dynInst->instAddr()));
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/gem5/src/cpu/o3/ |
H A D | dyn_inst_impl.hh | 52 BaseO3DynInst<Impl>::BaseO3DynInst(const StaticInstPtr &staticInst, argument 56 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu) 83 this->staticInst->disassemble(this->instAddr())); 138 this->fault = this->staticInst->execute(this, this->traceData); 156 this->fault = this->staticInst->initiateAcc(this, this->traceData); 180 this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); 191 this->cpu->trap(fault, this->threadNumber, this->staticInst);
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H A D | dyn_inst.hh | 81 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr 216 this->staticInst->destRegIdx(idx); 219 this->setIntRegOperand(this->staticInst.get(), idx, 223 this->setFloatRegOperandBits(this->staticInst.get(), idx, 227 this->setVecRegOperand(this->staticInst.get(), idx, 231 this->setVecElemOperand(this->staticInst.get(), idx, 235 this->setVecPredRegOperand(this->staticInst.get(), idx, 239 this->setCCRegOperand(this->staticInst.get(), idx,
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/gem5/src/sim/ |
H A D | insttracer.hh | 68 StaticInstPtr staticInst; member in class:Trace::InstRecord 154 : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc), 229 StaticInstPtr getStaticInst() const { return staticInst; } 260 const StaticInstPtr staticInst, TheISA::PCState pc,
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