11060SN/A/* 214025Sgiacomo.gabrielli@arm.com * Copyright (c) 2011, 2019 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142702SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151060SN/A * All rights reserved. 161060SN/A * 171060SN/A * Redistribution and use in source and binary forms, with or without 181060SN/A * modification, are permitted provided that the following conditions are 191060SN/A * met: redistributions of source code must retain the above copyright 201060SN/A * notice, this list of conditions and the following disclaimer; 211060SN/A * redistributions in binary form must reproduce the above copyright 221060SN/A * notice, this list of conditions and the following disclaimer in the 231060SN/A * documentation and/or other materials provided with the distribution; 241060SN/A * neither the name of the copyright holders nor the names of its 251060SN/A * contributors may be used to endorse or promote products derived from 261060SN/A * this software without specific prior written permission. 271060SN/A * 281060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Kevin Lim 411060SN/A */ 421060SN/A 439944Smatt.horsnell@ARM.com#ifndef __CPU_BASE_DYN_INST_IMPL_HH__ 449944Smatt.horsnell@ARM.com#define __CPU_BASE_DYN_INST_IMPL_HH__ 459944Smatt.horsnell@ARM.com 461060SN/A#include <iostream> 472292SN/A#include <set> 488229Snate@binkert.org#include <sstream> 491060SN/A#include <string> 501060SN/A 511060SN/A#include "base/cprintf.hh" 521061SN/A#include "base/trace.hh" 536658Snate@binkert.org#include "config/the_isa.hh" 546658Snate@binkert.org#include "cpu/base_dyn_inst.hh" 551060SN/A#include "cpu/exetrace.hh" 568232Snate@binkert.org#include "debug/DynInst.hh" 578232Snate@binkert.org#include "debug/IQ.hh" 582669SN/A#include "mem/request.hh" 596658Snate@binkert.org#include "sim/faults.hh" 601060SN/A 611061SN/Atemplate <class Impl> 6210417Sandreas.hansson@arm.comBaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst, 6310417Sandreas.hansson@arm.com const StaticInstPtr &_macroop, 647720Sgblack@eecs.umich.edu TheISA::PCState _pc, TheISA::PCState _predPC, 653794Sgblack@eecs.umich.edu InstSeqNum seq_num, ImplCPU *cpu) 6613453Srekai.gonzalezalberquilla@arm.com : staticInst(_staticInst), cpu(cpu), 6713453Srekai.gonzalezalberquilla@arm.com thread(nullptr), 6813453Srekai.gonzalezalberquilla@arm.com traceData(nullptr), 6913453Srekai.gonzalezalberquilla@arm.com macroop(_macroop), 7013453Srekai.gonzalezalberquilla@arm.com memData(nullptr), 7113453Srekai.gonzalezalberquilla@arm.com savedReq(nullptr), 7213453Srekai.gonzalezalberquilla@arm.com reqToVerify(nullptr) 731060SN/A{ 741464SN/A seqNum = seq_num; 751061SN/A 767720Sgblack@eecs.umich.edu pc = _pc; 777720Sgblack@eecs.umich.edu predPC = _predPC; 784636Sgblack@eecs.umich.edu 794636Sgblack@eecs.umich.edu initVars(); 804636Sgblack@eecs.umich.edu} 814636Sgblack@eecs.umich.edu 824636Sgblack@eecs.umich.edutemplate <class Impl> 8310417Sandreas.hansson@arm.comBaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst, 8410417Sandreas.hansson@arm.com const StaticInstPtr &_macroop) 859046SAli.Saidi@ARM.com : staticInst(_staticInst), traceData(NULL), macroop(_macroop) 861464SN/A{ 872292SN/A seqNum = 0; 881464SN/A initVars(); 891464SN/A} 901464SN/A 911464SN/Atemplate <class Impl> 921464SN/Avoid 931464SN/ABaseDynInst<Impl>::initVars() 941464SN/A{ 952678SN/A memData = NULL; 962669SN/A effAddr = 0; 9713590Srekai.gonzalezalberquilla@arm.com physEffAddr = 0; 981060SN/A readyRegs = 0; 9910031SAli.Saidi@ARM.com memReqFlags = 0; 1001060SN/A 1012731SN/A status.reset(); 1022731SN/A 1039046SAli.Saidi@ARM.com instFlags.reset(); 1049046SAli.Saidi@ARM.com instFlags[RecordResult] = true; 1059046SAli.Saidi@ARM.com instFlags[Predicate] = true; 10613953Sgiacomo.gabrielli@arm.com instFlags[MemAccPredicate] = true; 1072731SN/A 1082292SN/A lqIdx = -1; 1092292SN/A sqIdx = -1; 1102292SN/A 1111060SN/A // Eventually make this a parameter. 1121060SN/A threadNumber = 0; 1131464SN/A 1141060SN/A // Also make this a parameter, or perhaps get it from xc or cpu. 1151060SN/A asid = 0; 1161060SN/A 1172698SN/A // Initialize the fault to be NoFault. 1182292SN/A fault = NoFault; 1191060SN/A 1205737Scws3k@cs.virginia.edu#ifndef NDEBUG 1215737Scws3k@cs.virginia.edu ++cpu->instcount; 1221060SN/A 1235737Scws3k@cs.virginia.edu if (cpu->instcount > 1500) { 1245375Svilas.sridharan@gmail.com#ifdef DEBUG 1252292SN/A cpu->dumpInsts(); 1262292SN/A dumpSNList(); 1272292SN/A#endif 1285737Scws3k@cs.virginia.edu assert(cpu->instcount <= 1500); 1292292SN/A } 1302292SN/A 1315737Scws3k@cs.virginia.edu DPRINTF(DynInst, 1325737Scws3k@cs.virginia.edu "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n", 1335737Scws3k@cs.virginia.edu seqNum, cpu->name(), cpu->instcount); 1345737Scws3k@cs.virginia.edu#endif 1352292SN/A 1362292SN/A#ifdef DEBUG 1372292SN/A cpu->snList.insert(seqNum); 1382292SN/A#endif 1398733Sgeoffrey.blake@arm.com 1401060SN/A} 1411060SN/A 1421061SN/Atemplate <class Impl> 1431060SN/ABaseDynInst<Impl>::~BaseDynInst() 1441060SN/A{ 1452678SN/A if (memData) { 1462678SN/A delete [] memData; 1472292SN/A } 1482292SN/A 1492292SN/A if (traceData) { 1502292SN/A delete traceData; 1512292SN/A } 1522292SN/A 1532348SN/A fault = NoFault; 1542348SN/A 1555737Scws3k@cs.virginia.edu#ifndef NDEBUG 1565737Scws3k@cs.virginia.edu --cpu->instcount; 1572292SN/A 1585737Scws3k@cs.virginia.edu DPRINTF(DynInst, 1595737Scws3k@cs.virginia.edu "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n", 1605737Scws3k@cs.virginia.edu seqNum, cpu->name(), cpu->instcount); 1615737Scws3k@cs.virginia.edu#endif 1622292SN/A#ifdef DEBUG 1632292SN/A cpu->snList.erase(seqNum); 1642292SN/A#endif 1658733Sgeoffrey.blake@arm.com 1661060SN/A} 1671464SN/A 1682292SN/A#ifdef DEBUG 1692292SN/Atemplate <class Impl> 1702292SN/Avoid 1712292SN/ABaseDynInst<Impl>::dumpSNList() 1722292SN/A{ 1732292SN/A std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); 1742292SN/A 1752292SN/A int count = 0; 1762292SN/A while (sn_it != cpu->snList.end()) { 1772292SN/A cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it)); 1782292SN/A count++; 1792292SN/A sn_it++; 1802292SN/A } 1812292SN/A} 1822292SN/A#endif 1832292SN/A 1841061SN/Atemplate <class Impl> 1851060SN/Avoid 1861060SN/ABaseDynInst<Impl>::dump() 1871060SN/A{ 1887720Sgblack@eecs.umich.edu cprintf("T%d : %#08d `", threadNumber, pc.instAddr()); 1897720Sgblack@eecs.umich.edu std::cout << staticInst->disassemble(pc.instAddr()); 1901060SN/A cprintf("'\n"); 1911060SN/A} 1921060SN/A 1931061SN/Atemplate <class Impl> 1941060SN/Avoid 1951060SN/ABaseDynInst<Impl>::dump(std::string &outstring) 1961060SN/A{ 1971060SN/A std::ostringstream s; 1987720Sgblack@eecs.umich.edu s << "T" << threadNumber << " : 0x" << pc.instAddr() << " " 1997720Sgblack@eecs.umich.edu << staticInst->disassemble(pc.instAddr()); 2001060SN/A 2011060SN/A outstring = s.str(); 2021060SN/A} 2031060SN/A 2041464SN/Atemplate <class Impl> 2052292SN/Avoid 2062292SN/ABaseDynInst<Impl>::markSrcRegReady() 2072292SN/A{ 2087599Sminkyu.jeong@arm.com DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n", 2097599Sminkyu.jeong@arm.com seqNum, readyRegs+1, numSrcRegs(), readyToIssue()); 2102292SN/A if (++readyRegs == numSrcRegs()) { 2114032Sktlim@umich.edu setCanIssue(); 2122292SN/A } 2132292SN/A} 2142292SN/A 2152292SN/Atemplate <class Impl> 2162292SN/Avoid 2172292SN/ABaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx) 2182292SN/A{ 2192292SN/A _readySrcRegIdx[src_idx] = true; 2202292SN/A 2212731SN/A markSrcRegReady(); 2222292SN/A} 2232292SN/A 2242292SN/Atemplate <class Impl> 2251464SN/Abool 22613429Srekai.gonzalezalberquilla@arm.comBaseDynInst<Impl>::eaSrcsReady() const 2271464SN/A{ 2281464SN/A // For now I am assuming that src registers 1..n-1 are the ones that the 2291464SN/A // EA calc depends on. (i.e. src reg 0 is the source of the data to be 2301464SN/A // stored) 2311464SN/A 2322292SN/A for (int i = 1; i < numSrcRegs(); ++i) { 2331464SN/A if (!_readySrcRegIdx[i]) 2341464SN/A return false; 2351464SN/A } 2361464SN/A 2371464SN/A return true; 2381464SN/A} 2399944Smatt.horsnell@ARM.com 24014025Sgiacomo.gabrielli@arm.com 24114025Sgiacomo.gabrielli@arm.com 24214025Sgiacomo.gabrielli@arm.comtemplate <class Impl> 24314025Sgiacomo.gabrielli@arm.comvoid 24414025Sgiacomo.gabrielli@arm.comBaseDynInst<Impl>::setSquashed() 24514025Sgiacomo.gabrielli@arm.com{ 24614025Sgiacomo.gabrielli@arm.com status.set(Squashed); 24714025Sgiacomo.gabrielli@arm.com 24814025Sgiacomo.gabrielli@arm.com if (!isPinnedRegsRenamed() || isPinnedRegsSquashDone()) 24914025Sgiacomo.gabrielli@arm.com return; 25014025Sgiacomo.gabrielli@arm.com 25114025Sgiacomo.gabrielli@arm.com // This inst has been renamed already so it may go through rename 25214025Sgiacomo.gabrielli@arm.com // again (e.g. if the squash is due to memory access order violation). 25314025Sgiacomo.gabrielli@arm.com // Reset the write counters for all pinned destination register to ensure 25414025Sgiacomo.gabrielli@arm.com // that they are in a consistent state for a possible re-rename. This also 25514025Sgiacomo.gabrielli@arm.com // ensures that dest regs will be pinned to the same phys register if 25614025Sgiacomo.gabrielli@arm.com // re-rename happens. 25714025Sgiacomo.gabrielli@arm.com for (int idx = 0; idx < numDestRegs(); idx++) { 25814025Sgiacomo.gabrielli@arm.com PhysRegIdPtr phys_dest_reg = renamedDestRegIdx(idx); 25914025Sgiacomo.gabrielli@arm.com if (phys_dest_reg->isPinned()) { 26014025Sgiacomo.gabrielli@arm.com phys_dest_reg->incrNumPinnedWrites(); 26114025Sgiacomo.gabrielli@arm.com if (isPinnedRegsWritten()) 26214025Sgiacomo.gabrielli@arm.com phys_dest_reg->incrNumPinnedWritesToComplete(); 26314025Sgiacomo.gabrielli@arm.com } 26414025Sgiacomo.gabrielli@arm.com } 26514025Sgiacomo.gabrielli@arm.com setPinnedRegsSquashDone(); 26614025Sgiacomo.gabrielli@arm.com} 26714025Sgiacomo.gabrielli@arm.com 26814025Sgiacomo.gabrielli@arm.com 26914025Sgiacomo.gabrielli@arm.com 2709944Smatt.horsnell@ARM.com#endif//__CPU_BASE_DYN_INST_IMPL_HH__ 271