/gem5/src/systemc/tests/tlm/nb2b_adapter/ |
H A D | mm.h | 32 access* x = empties; 35 // Delete free list access struct 44 struct access struct in class:mm 47 access* next; 48 access* prev; 51 access* free_list; 52 access* empties; 76 empties = new access;
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/gem5/src/systemc/tests/tlm/update_original/ |
H A D | mm.h | 32 access* x = empties; 35 // Delete free list access struct 44 struct access struct in class:mm 47 access* next; 48 access* prev; 51 access* free_list; 52 access* empties; 76 empties = new access;
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/gem5/src/arch/mips/ |
H A D | system.cc | 62 MipsSystem::setMipsAccess(Addr access) argument
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H A D | system.hh | 62 void setMipsAccess(Addr access);
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/gem5/src/arch/riscv/ |
H A D | system.cc | 66 RiscvSystem::setRiscvAccess(Addr access) argument
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H A D | system.hh | 75 void setRiscvAccess(Addr access);
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/gem5/ext/mcpat/ |
H A D | cacheunit.cc | 134 arrayPtr->tdp_stats.readAc.access = cache_stats.tdp_read_access_scalar * 138 arrayPtr->tdp_stats.readAc.hit = arrayPtr->tdp_stats.readAc.access - 140 arrayPtr->tdp_stats.writeAc.access = cache_stats.tdp_write_access_scalar * 144 arrayPtr->tdp_stats.writeAc.hit = arrayPtr->tdp_stats.writeAc.access - 146 arrayPtr->tdp_stats.searchAc.access = 0; 152 arrayPtr->rtp_stats.dataReadAc.access = 154 arrayPtr->rtp_stats.dataWriteAc.access = 156 arrayPtr->rtp_stats.tagReadAc.access = 158 arrayPtr->rtp_stats.tagWriteAc.access = 166 arrayPtr->rtp_stats.dataReadAc.access [all...] |
H A D | memoryctrl.cc | 82 tdp_stats.readAc.access = 0.5 * mcp.num_channels * mcp.clockRate; 83 tdp_stats.writeAc.access = 0.5 * mcp.num_channels * mcp.clockRate; 85 rtp_stats.readAc.access = mcs.reads; 86 rtp_stats.writeAc.access = mcs.writes; 127 //per access energy in memory controller 191 (tdp_stats.readAc.access + tdp_stats.writeAc.access); 196 (rtp_stats.readAc.access + rtp_stats.writeAc.access) * 212 tdp_stats.readAc.access [all...] |
H A D | core.cc | 131 * look up table than a cache with cache controller. When access miss, no load from other places 2178 // ASSUMPTION: All instructions access the branch predictors at Fetch and 2184 globalBPT->tdp_stats.readAc.access = tdp_read_accesses; 2185 globalBPT->tdp_stats.writeAc.access = 0; 2187 globalBPT->rtp_stats.readAc.access = core_stats.total_instructions; 2188 globalBPT->rtp_stats.writeAc.access = core_stats.branch_instructions; 2192 globalBPT->tdp_stats.readAc.access + 2194 globalBPT->tdp_stats.writeAc.access; 2200 globalBPT->rtp_stats.readAc.access + 2202 globalBPT->rtp_stats.writeAc.access; [all...] |
H A D | cachearray.cc | 285 rtp_stats.dataReadAc.access + 287 rtp_stats.dataWriteAc.access + 289 rtp_stats.tagReadAc.access + 291 rtp_stats.tagWriteAc.access) * l_ip.assoc; 295 local_result.power.readOp.dynamic * tdp_stats.readAc.access + 296 local_result.power.writeOp.dynamic * tdp_stats.writeAc.access + 297 local_result.power.searchOp.dynamic * tdp_stats.searchAc.access; 302 local_result.power.readOp.dynamic * rtp_stats.readAc.access + 303 local_result.power.writeOp.dynamic * rtp_stats.writeAc.access + 304 local_result.power.searchOp.dynamic * rtp_stats.searchAc.access; [all...] |
H A D | noc.cc | 121 tdp_stats.readAc.access = noc_stats.duty_cycle; 125 set_pppm(pppm_t, 1 * tdp_stats.readAc.access, 1, 1, 1); 151 rtp_stats.readAc.access = noc_stats.total_access; 157 router->buffer.power.writeOp.dynamic) * rtp_stats.readAc.access; 159 router->crossbar.power.readOp.dynamic * rtp_stats.readAc.access; 161 router->arbiter.power.readOp.dynamic * rtp_stats.readAc.access;
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H A D | basic_components.h | 116 double access; member in class:statsComponents 120 statsComponents() : access(0), hit(0), miss(0) {} 125 access = rhs.access; 131 access = 0;
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H A D | basic_components.cc | 328 z.access = x.access + y.access; 338 z.access = x.access * y[0];
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/gem5/src/cpu/simple/ |
H A D | noncaching.cc | 60 system->getPhysMem().access(pkt);
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/gem5/src/mem/cache/compressors/ |
H A D | bdi.hh | 226 virtual uint64_t access(const int index) const = 0; 266 uint64_t access(const int index) const override; 301 uint64_t access(const int index) const override; 343 uint64_t access(const int index) const override; 416 uint64_t access(const int index) const override;
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | access.S | 4 # access.S 7 # Test access-exception behavior. 24 # after the pc is set to rs1, an access exception should be raised.
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/gem5/src/arch/alpha/ |
H A D | system.hh | 73 void setAlphaAccess(Addr access);
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H A D | system.cc | 211 AlphaSystem::setAlphaAccess(Addr access) argument 215 virtProxy.write(addr, htog(Phys2K0Seg(access)));
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/gem5/util/ |
H A D | minorview.py | 78 if args.picture and os.access(args.picture, os.O_RDONLY): 98 if args.eventFile and os.access(args.eventFile, os.O_RDONLY):
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/gem5/src/cpu/ |
H A D | timebuf.hh | 134 T &operator*() const { return *buffer->access(index); } 135 T *operator->() const { return buffer->access(index); } 211 T *access(int idx) function in class:TimeBuffer
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/gem5/src/mem/cache/prefetch/ |
H A D | sbooe.cc | 71 SBOOEPrefetcher::access(Addr access_line) function in class:SBOOEPrefetcher 102 // (4) Calculate the new average access latency 136 const bool evaluationFinished = access(pfi_line);
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H A D | sbooe.hh | 70 * calculate the average access latency which is later used to 75 /** Holds the current average access latency */ 119 * @param tick Tick in which the access is expected to be filled 141 * Process an access to the specified line address and update the 146 bool access(Addr line);
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/gem5/ext/pybind11/tests/ |
H A D | test_methods_and_attributes.py | 223 @pytest.mark.parametrize("access", ["ro", "rw", "static_ro", "static_rw"]) 224 def test_property_return_value_policies(access): 225 if not access.startswith("static"): 230 ref = getattr(obj, access + "_ref") 233 assert getattr(obj, access + "_ref").value == 2 236 copy = getattr(obj, access + "_copy") 239 assert getattr(obj, access + "_copy").value == 1 241 copy = getattr(obj, access + "_func") 244 assert getattr(obj, access + "_func").value == 1
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/gem5/src/mem/ |
H A D | physical.hh | 204 * access. Note that memory in the guest should be accessed using 205 * access() or functionalAccess(). This interface is primarily 218 * Perform an untimed memory access and update all the state 222 * @param pkt Packet performing the access 224 void access(PacketPtr pkt); 229 * access. In addition to normal accesses this also facilitates 232 * @param pkt Packet performing the access
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/gem5/src/mem/cache/ |
H A D | noncoherent_cache.hh | 74 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
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