110152Satgutier@umich.edu/***************************************************************************** 210152Satgutier@umich.edu * McPAT 310152Satgutier@umich.edu * SOFTWARE LICENSE AGREEMENT 410152Satgutier@umich.edu * Copyright 2012 Hewlett-Packard Development Company, L.P. 510234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 610152Satgutier@umich.edu * All Rights Reserved 710152Satgutier@umich.edu * 810152Satgutier@umich.edu * Redistribution and use in source and binary forms, with or without 910152Satgutier@umich.edu * modification, are permitted provided that the following conditions are 1010152Satgutier@umich.edu * met: redistributions of source code must retain the above copyright 1110152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer; 1210152Satgutier@umich.edu * redistributions in binary form must reproduce the above copyright 1310152Satgutier@umich.edu * notice, this list of conditions and the following disclaimer in the 1410152Satgutier@umich.edu * documentation and/or other materials provided with the distribution; 1510152Satgutier@umich.edu * neither the name of the copyright holders nor the names of its 1610152Satgutier@umich.edu * contributors may be used to endorse or promote products derived from 1710152Satgutier@umich.edu * this software without specific prior written permission. 1810152Satgutier@umich.edu 1910152Satgutier@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2010152Satgutier@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2110152Satgutier@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2210152Satgutier@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2310152Satgutier@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2410152Satgutier@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2510152Satgutier@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2610152Satgutier@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2710152Satgutier@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2810152Satgutier@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2910234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3010152Satgutier@umich.edu * 3110152Satgutier@umich.edu ***************************************************************************/ 3210152Satgutier@umich.edu 3310152Satgutier@umich.edu#ifndef BASIC_COMPONENTS_H_ 3410152Satgutier@umich.edu#define BASIC_COMPONENTS_H_ 3510152Satgutier@umich.edu 3610152Satgutier@umich.edu#include <vector> 3710152Satgutier@umich.edu 3810234Syasuko.eckert@amd.com#include "component.h" 3910152Satgutier@umich.edu#include "parameter.h" 4010234Syasuko.eckert@amd.com#include "xmlParser.h" 4110152Satgutier@umich.edu 4210234Syasuko.eckert@amd.com/** 4310234Syasuko.eckert@amd.com * TODO: Since revisions to McPAT aim to make the component hierarchy more 4410234Syasuko.eckert@amd.com * modular, many of the parameter and statistics classes/structs included in 4510234Syasuko.eckert@amd.com * this file should be moved to the files for their respective components. 4610234Syasuko.eckert@amd.com */ 4710152Satgutier@umich.educonst double cdb_overhead = 1.1; 4810152Satgutier@umich.edu 4910152Satgutier@umich.eduenum FU_type { 5010152Satgutier@umich.edu FPU, 5110152Satgutier@umich.edu ALU, 5210152Satgutier@umich.edu MUL 5310152Satgutier@umich.edu}; 5410152Satgutier@umich.edu 5510152Satgutier@umich.eduenum Core_type { 5610234Syasuko.eckert@amd.com OOO, 5710234Syasuko.eckert@amd.com Inorder 5810152Satgutier@umich.edu}; 5910152Satgutier@umich.edu 6010152Satgutier@umich.eduenum Renaming_type { 6110152Satgutier@umich.edu RAMbased, 6210234Syasuko.eckert@amd.com CAMbased 6310152Satgutier@umich.edu}; 6410152Satgutier@umich.edu 6510152Satgutier@umich.eduenum Scheduler_type { 6610152Satgutier@umich.edu PhysicalRegFile, 6710234Syasuko.eckert@amd.com ReservationStation 6810152Satgutier@umich.edu}; 6910152Satgutier@umich.edu 7010234Syasuko.eckert@amd.comenum Cache_type { 7110234Syasuko.eckert@amd.com DATA_CACHE, 7210234Syasuko.eckert@amd.com INSTRUCTION_CACHE, 7310234Syasuko.eckert@amd.com MIXED 7410234Syasuko.eckert@amd.com}; 7510234Syasuko.eckert@amd.com 7610234Syasuko.eckert@amd.comenum CacheLevel { 7710234Syasuko.eckert@amd.com L1, 7810152Satgutier@umich.edu L2, 7910152Satgutier@umich.edu L3, 8010152Satgutier@umich.edu L1Directory, 8110152Satgutier@umich.edu L2Directory 8210152Satgutier@umich.edu}; 8310152Satgutier@umich.edu 8410152Satgutier@umich.eduenum MemoryCtrl_type { 8510234Syasuko.eckert@amd.com MC, //memory controller 8610234Syasuko.eckert@amd.com FLASHC //flash controller 8710152Satgutier@umich.edu}; 8810152Satgutier@umich.edu 8910152Satgutier@umich.eduenum Dir_type { 9010234Syasuko.eckert@amd.com ST,//shadowed tag 9110234Syasuko.eckert@amd.com DC,//directory cache 9210234Syasuko.eckert@amd.com SBT,//static bank tag 9310234Syasuko.eckert@amd.com NonDir 9410152Satgutier@umich.edu 9510152Satgutier@umich.edu}; 9610152Satgutier@umich.edu 9710152Satgutier@umich.eduenum Cache_policy { 9810234Syasuko.eckert@amd.com Write_through, 9910234Syasuko.eckert@amd.com Write_back 10010152Satgutier@umich.edu}; 10110152Satgutier@umich.edu 10210152Satgutier@umich.eduenum Device_ty { 10310234Syasuko.eckert@amd.com Core_device, 10410234Syasuko.eckert@amd.com Uncore_device, 10510234Syasuko.eckert@amd.com LLC_device 10610152Satgutier@umich.edu}; 10710152Satgutier@umich.edu 10810234Syasuko.eckert@amd.comenum Access_mode { 10910234Syasuko.eckert@amd.com Normal, 11010234Syasuko.eckert@amd.com Sequential, 11110234Syasuko.eckert@amd.com Fast 11210234Syasuko.eckert@amd.com}; 11310234Syasuko.eckert@amd.com 11410234Syasuko.eckert@amd.comclass statsComponents { 11510234Syasuko.eckert@amd.compublic: 11610152Satgutier@umich.edu double access; 11710152Satgutier@umich.edu double hit; 11810152Satgutier@umich.edu double miss; 11910152Satgutier@umich.edu 12010152Satgutier@umich.edu statsComponents() : access(0), hit(0), miss(0) {} 12110234Syasuko.eckert@amd.com statsComponents(const statsComponents & obj) { 12210234Syasuko.eckert@amd.com *this = obj; 12310152Satgutier@umich.edu } 12410234Syasuko.eckert@amd.com statsComponents & operator=(const statsComponents & rhs) { 12510234Syasuko.eckert@amd.com access = rhs.access; 12610234Syasuko.eckert@amd.com hit = rhs.hit; 12710234Syasuko.eckert@amd.com miss = rhs.miss; 12810234Syasuko.eckert@amd.com return *this; 12910234Syasuko.eckert@amd.com } 13010234Syasuko.eckert@amd.com void reset() { 13110234Syasuko.eckert@amd.com access = 0; 13210234Syasuko.eckert@amd.com hit = 0; 13310234Syasuko.eckert@amd.com miss = 0; 13410234Syasuko.eckert@amd.com } 13510152Satgutier@umich.edu 13610234Syasuko.eckert@amd.com friend statsComponents operator+(const statsComponents & x, 13710234Syasuko.eckert@amd.com const statsComponents & y); 13810234Syasuko.eckert@amd.com friend statsComponents operator*(const statsComponents & x, 13910234Syasuko.eckert@amd.com double const * const y); 14010152Satgutier@umich.edu}; 14110152Satgutier@umich.edu 14210234Syasuko.eckert@amd.comclass statsDef { 14310234Syasuko.eckert@amd.compublic: 14410152Satgutier@umich.edu statsComponents readAc; 14510152Satgutier@umich.edu statsComponents writeAc; 14610152Satgutier@umich.edu statsComponents searchAc; 14710234Syasuko.eckert@amd.com statsComponents dataReadAc; 14810234Syasuko.eckert@amd.com statsComponents dataWriteAc; 14910234Syasuko.eckert@amd.com statsComponents tagReadAc; 15010234Syasuko.eckert@amd.com statsComponents tagWriteAc; 15110152Satgutier@umich.edu 15210234Syasuko.eckert@amd.com statsDef() : readAc(), writeAc(), searchAc() { } 15310234Syasuko.eckert@amd.com void reset() { 15410234Syasuko.eckert@amd.com readAc.reset(); 15510234Syasuko.eckert@amd.com writeAc.reset(); 15610234Syasuko.eckert@amd.com searchAc.reset(); 15710234Syasuko.eckert@amd.com } 15810152Satgutier@umich.edu 15910152Satgutier@umich.edu friend statsDef operator+(const statsDef & x, const statsDef & y); 16010152Satgutier@umich.edu friend statsDef operator*(const statsDef & x, double const * const y); 16110152Satgutier@umich.edu}; 16210152Satgutier@umich.edu 16310234Syasuko.eckert@amd.com/** 16410234Syasuko.eckert@amd.com * An object to store the computed data that will be output from McPAT on a 16510234Syasuko.eckert@amd.com * per-component-instance basis. Currently, this includes the amount of storage 16610234Syasuko.eckert@amd.com * that the component comprises, its chip area, and power and energy 16710234Syasuko.eckert@amd.com * calculations. 16810234Syasuko.eckert@amd.com */ 16910234Syasuko.eckert@amd.comclass McPATOutput { 17010234Syasuko.eckert@amd.compublic: 17110234Syasuko.eckert@amd.com // Storage is in bytes (B) 17210234Syasuko.eckert@amd.com double storage; 17310234Syasuko.eckert@amd.com // Area is in mm^2 17410234Syasuko.eckert@amd.com double area; 17510234Syasuko.eckert@amd.com // Peak Dynamic Power is in W 17610234Syasuko.eckert@amd.com double peak_dynamic_power; 17710234Syasuko.eckert@amd.com // Subthreshold Leakage Power is in W 17810234Syasuko.eckert@amd.com double subthreshold_leakage_power; 17910234Syasuko.eckert@amd.com // Gate Leakage Power is in W 18010234Syasuko.eckert@amd.com double gate_leakage_power; 18110234Syasuko.eckert@amd.com // Runtime Dynamic Energy is in J 18210234Syasuko.eckert@amd.com double runtime_dynamic_energy; 18310152Satgutier@umich.edu 18410234Syasuko.eckert@amd.com void reset(); 18510234Syasuko.eckert@amd.com 18610234Syasuko.eckert@amd.com friend McPATOutput operator+(const McPATOutput &lhs, const McPATOutput &rhs); 18710234Syasuko.eckert@amd.com void operator+=(const McPATOutput &rhs); 18810152Satgutier@umich.edu}; 18910152Satgutier@umich.edu 19010234Syasuko.eckert@amd.com/** 19110234Syasuko.eckert@amd.com * A McPATComponent encompasses all the parts that are common to any component 19210234Syasuko.eckert@amd.com * for which McPAT may compute and print power, area, and timing data. It 19310234Syasuko.eckert@amd.com * includes a pointer to the XML data from which the component gathers its 19410234Syasuko.eckert@amd.com * input parameters, it stores the variables that are commonly used in all 19510234Syasuko.eckert@amd.com * components, and it maintains the hierarchical structure to recursively 19610234Syasuko.eckert@amd.com * compute and print output. This is a base class from which all components 19710234Syasuko.eckert@amd.com * should inherit these functionality (possibly through other descended 19810234Syasuko.eckert@amd.com * classes. 19910234Syasuko.eckert@amd.com*/ 20010234Syasuko.eckert@amd.comclass McPATComponent : public Component { 20110152Satgutier@umich.edupublic: 20210234Syasuko.eckert@amd.com static bool debug; 20310234Syasuko.eckert@amd.com 20410234Syasuko.eckert@amd.com // Variables shared across the system by all McPATComponents 20510234Syasuko.eckert@amd.com static bool opt_for_clk; 20610234Syasuko.eckert@amd.com static int longer_channel_device; 20710234Syasuko.eckert@amd.com static double execution_time; 20810234Syasuko.eckert@amd.com static int physical_address_width; 20910234Syasuko.eckert@amd.com static int virtual_address_width; 21010234Syasuko.eckert@amd.com static int virtual_memory_page_size; 21110234Syasuko.eckert@amd.com static int data_path_width; 21210234Syasuko.eckert@amd.com 21310234Syasuko.eckert@amd.com // Although these two variables are static right now, they need to be 21410234Syasuko.eckert@amd.com // modulated on a per-frequency-domain basis eventually. 21510234Syasuko.eckert@amd.com static double target_core_clockrate; 21610234Syasuko.eckert@amd.com static double total_cycles; 21710234Syasuko.eckert@amd.com 21810234Syasuko.eckert@amd.com XMLNode* xml_data; 21910234Syasuko.eckert@amd.com InputParameter interface_ip; 22010152Satgutier@umich.edu string name; 22110234Syasuko.eckert@amd.com // Number of cycles per second (consider changing name) 22210234Syasuko.eckert@amd.com double clockRate; 22310234Syasuko.eckert@amd.com vector<McPATComponent*> children; 22410234Syasuko.eckert@amd.com // The data structure that is printed in displayData 22510234Syasuko.eckert@amd.com McPATOutput output_data; 22610234Syasuko.eckert@amd.com // Set this to contain the stats to calculate peak dynamic power 22710234Syasuko.eckert@amd.com statsDef tdp_stats; 22810234Syasuko.eckert@amd.com // Set this to contain the stats to calculate runtime dynamic energy/power 22910234Syasuko.eckert@amd.com statsDef rtp_stats; 23010234Syasuko.eckert@amd.com // Holds the peak dynamic power calculation 23110234Syasuko.eckert@amd.com powerDef power_t; 23210234Syasuko.eckert@amd.com // Holds the runtime dynamic power calculation 23310234Syasuko.eckert@amd.com powerDef rt_power; 23410234Syasuko.eckert@amd.com 23510234Syasuko.eckert@amd.com McPATComponent(); 23610234Syasuko.eckert@amd.com // Which of these is a better way of doing things?! 23710234Syasuko.eckert@amd.com McPATComponent(XMLNode* _xml_data); 23810234Syasuko.eckert@amd.com McPATComponent(XMLNode* _xml_data, InputParameter* _interface_ip); 23910234Syasuko.eckert@amd.com virtual void recursiveInstantiate(); 24010234Syasuko.eckert@amd.com virtual void computeArea(); 24110234Syasuko.eckert@amd.com // This function should probably be pure virtual, but it's too early in 24210234Syasuko.eckert@amd.com // the modifying process to know for sure. Note that each component has 24310234Syasuko.eckert@amd.com // to calculate it's own power consumption 24410234Syasuko.eckert@amd.com virtual void computeEnergy(); 24510234Syasuko.eckert@amd.com virtual void displayData(uint32_t indent, int plevel); 24610234Syasuko.eckert@amd.com ~McPATComponent(); 24710234Syasuko.eckert@amd.com 24810234Syasuko.eckert@amd.com protected: 24910234Syasuko.eckert@amd.com void errorUnspecifiedParam(string param); 25010234Syasuko.eckert@amd.com void errorNonPositiveParam(string param); 25110234Syasuko.eckert@amd.com void warnUnrecognizedComponent(XMLCSTR component); 25210234Syasuko.eckert@amd.com void warnUnrecognizedParam(XMLCSTR param); 25310234Syasuko.eckert@amd.com void warnUnrecognizedStat(XMLCSTR stat); 25410234Syasuko.eckert@amd.com void warnIncompleteComponentType(XMLCSTR type); 25510234Syasuko.eckert@amd.com void warnMissingComponentType(XMLCSTR id); 25610234Syasuko.eckert@amd.com void warnMissingParamName(XMLCSTR id); 25710234Syasuko.eckert@amd.com void warnMissingStatName(XMLCSTR id); 25810152Satgutier@umich.edu}; 25910152Satgutier@umich.edu 26010234Syasuko.eckert@amd.comdouble longer_channel_device_reduction( 26110234Syasuko.eckert@amd.com enum Device_ty device_ty = Core_device, 26210234Syasuko.eckert@amd.com enum Core_type core_ty = Inorder); 26310234Syasuko.eckert@amd.com 26410234Syasuko.eckert@amd.comclass CoreParameters { 26510152Satgutier@umich.edupublic: 26610234Syasuko.eckert@amd.com bool opt_local; 26710234Syasuko.eckert@amd.com bool x86; 26810234Syasuko.eckert@amd.com bool Embedded; 26910234Syasuko.eckert@amd.com enum Core_type core_ty; 27010234Syasuko.eckert@amd.com enum Renaming_type rm_ty; 27110234Syasuko.eckert@amd.com enum Scheduler_type scheu_ty; 27210234Syasuko.eckert@amd.com double clockRate; 27310234Syasuko.eckert@amd.com int arch_ireg_width; 27410234Syasuko.eckert@amd.com int arch_freg_width; 27510234Syasuko.eckert@amd.com int archi_Regs_IRF_size; 27610234Syasuko.eckert@amd.com int archi_Regs_FRF_size; 27710234Syasuko.eckert@amd.com int phy_ireg_width; 27810234Syasuko.eckert@amd.com int phy_freg_width; 27910234Syasuko.eckert@amd.com int num_IRF_entry; 28010234Syasuko.eckert@amd.com int num_FRF_entry; 28110234Syasuko.eckert@amd.com int num_ifreelist_entries; 28210234Syasuko.eckert@amd.com int num_ffreelist_entries; 28310234Syasuko.eckert@amd.com int fetchW; 28410234Syasuko.eckert@amd.com int decodeW; 28510234Syasuko.eckert@amd.com int issueW; 28610234Syasuko.eckert@amd.com int peak_issueW; 28710234Syasuko.eckert@amd.com int commitW; 28810234Syasuko.eckert@amd.com int peak_commitW; 28910234Syasuko.eckert@amd.com int predictionW; 29010234Syasuko.eckert@amd.com int fp_issueW; 29110234Syasuko.eckert@amd.com int fp_decodeW; 29210234Syasuko.eckert@amd.com int perThreadState; 29310234Syasuko.eckert@amd.com int globalCheckpoint; 29410234Syasuko.eckert@amd.com int instruction_length; 29510234Syasuko.eckert@amd.com int pc_width; 29610234Syasuko.eckert@amd.com int opcode_width; 29710234Syasuko.eckert@amd.com int micro_opcode_length; 29810234Syasuko.eckert@amd.com int num_hthreads; 29910234Syasuko.eckert@amd.com int pipeline_stages; 30010234Syasuko.eckert@amd.com int fp_pipeline_stages; 30110234Syasuko.eckert@amd.com int num_pipelines; 30210234Syasuko.eckert@amd.com int num_fp_pipelines; 30310234Syasuko.eckert@amd.com int num_alus; 30410234Syasuko.eckert@amd.com int num_muls; 30510234Syasuko.eckert@amd.com double num_fpus; 30610234Syasuko.eckert@amd.com int int_data_width; 30710234Syasuko.eckert@amd.com int fp_data_width; 30810234Syasuko.eckert@amd.com int v_address_width; 30910234Syasuko.eckert@amd.com int p_address_width; 31010234Syasuko.eckert@amd.com bool regWindowing; 31110234Syasuko.eckert@amd.com bool multithreaded; 31210234Syasuko.eckert@amd.com double pppm_lkg_multhread[4]; 31310234Syasuko.eckert@amd.com int ROB_size; 31410234Syasuko.eckert@amd.com int ROB_assoc; 31510234Syasuko.eckert@amd.com int ROB_nbanks; 31610234Syasuko.eckert@amd.com int ROB_tag_width; 31710234Syasuko.eckert@amd.com int scheduler_assoc; 31810234Syasuko.eckert@amd.com int scheduler_nbanks; 31910234Syasuko.eckert@amd.com int register_window_size; 32010234Syasuko.eckert@amd.com double register_window_throughput; 32110234Syasuko.eckert@amd.com double register_window_latency; 32210234Syasuko.eckert@amd.com int register_window_assoc; 32310234Syasuko.eckert@amd.com int register_window_nbanks; 32410234Syasuko.eckert@amd.com int register_window_tag_width; 32510234Syasuko.eckert@amd.com int register_window_rw_ports; 32610234Syasuko.eckert@amd.com int phy_Regs_IRF_size; 32710234Syasuko.eckert@amd.com int phy_Regs_IRF_assoc; 32810234Syasuko.eckert@amd.com int phy_Regs_IRF_nbanks; 32910234Syasuko.eckert@amd.com int phy_Regs_IRF_tag_width; 33010234Syasuko.eckert@amd.com int phy_Regs_IRF_rd_ports; 33110234Syasuko.eckert@amd.com int phy_Regs_IRF_wr_ports; 33210234Syasuko.eckert@amd.com int phy_Regs_FRF_size; 33310234Syasuko.eckert@amd.com int phy_Regs_FRF_assoc; 33410234Syasuko.eckert@amd.com int phy_Regs_FRF_nbanks; 33510234Syasuko.eckert@amd.com int phy_Regs_FRF_tag_width; 33610234Syasuko.eckert@amd.com int phy_Regs_FRF_rd_ports; 33710234Syasuko.eckert@amd.com int phy_Regs_FRF_wr_ports; 33810234Syasuko.eckert@amd.com int front_rat_nbanks; 33910234Syasuko.eckert@amd.com int front_rat_rw_ports; 34010234Syasuko.eckert@amd.com int retire_rat_nbanks; 34110234Syasuko.eckert@amd.com int retire_rat_rw_ports; 34210234Syasuko.eckert@amd.com int freelist_nbanks; 34310234Syasuko.eckert@amd.com int freelist_rw_ports; 34410234Syasuko.eckert@amd.com int memory_ports; 34510234Syasuko.eckert@amd.com int load_buffer_size; 34610234Syasuko.eckert@amd.com int load_buffer_assoc; 34710234Syasuko.eckert@amd.com int load_buffer_nbanks; 34810234Syasuko.eckert@amd.com int store_buffer_size; 34910234Syasuko.eckert@amd.com int store_buffer_assoc; 35010234Syasuko.eckert@amd.com int store_buffer_nbanks; 35110234Syasuko.eckert@amd.com int instruction_window_size; 35210234Syasuko.eckert@amd.com int fp_instruction_window_size; 35310234Syasuko.eckert@amd.com int instruction_buffer_size; 35410234Syasuko.eckert@amd.com int instruction_buffer_assoc; 35510234Syasuko.eckert@amd.com int instruction_buffer_nbanks; 35610234Syasuko.eckert@amd.com int instruction_buffer_tag_width; 35710234Syasuko.eckert@amd.com int number_instruction_fetch_ports; 35810234Syasuko.eckert@amd.com int RAS_size; 35910234Syasuko.eckert@amd.com int execu_int_bypass_ports; 36010234Syasuko.eckert@amd.com int execu_mul_bypass_ports; 36110234Syasuko.eckert@amd.com int execu_fp_bypass_ports; 36210234Syasuko.eckert@amd.com Wire_type execu_bypass_wire_type; 36310234Syasuko.eckert@amd.com Wire_type execu_broadcast_wt; 36410234Syasuko.eckert@amd.com int execu_wire_mat_type; 36510234Syasuko.eckert@amd.com double execu_bypass_base_width; 36610234Syasuko.eckert@amd.com double execu_bypass_base_height; 36710234Syasuko.eckert@amd.com int execu_bypass_start_wiring_level; 36810234Syasuko.eckert@amd.com double execu_bypass_route_over_perc; 36910234Syasuko.eckert@amd.com double broadcast_numerator; 37010152Satgutier@umich.edu}; 37110152Satgutier@umich.edu 37210234Syasuko.eckert@amd.comclass CoreStatistics { 37310152Satgutier@umich.edupublic: 37410234Syasuko.eckert@amd.com double pipeline_duty_cycle; 37510234Syasuko.eckert@amd.com double total_cycles; 37610234Syasuko.eckert@amd.com double busy_cycles; 37710234Syasuko.eckert@amd.com double idle_cycles; 37810234Syasuko.eckert@amd.com double IFU_duty_cycle; 37910234Syasuko.eckert@amd.com double BR_duty_cycle; 38010234Syasuko.eckert@amd.com double LSU_duty_cycle; 38110234Syasuko.eckert@amd.com double MemManU_I_duty_cycle; 38210234Syasuko.eckert@amd.com double MemManU_D_duty_cycle; 38310234Syasuko.eckert@amd.com double ALU_duty_cycle; 38410234Syasuko.eckert@amd.com double MUL_duty_cycle; 38510234Syasuko.eckert@amd.com double FPU_duty_cycle; 38610234Syasuko.eckert@amd.com double ALU_cdb_duty_cycle; 38710234Syasuko.eckert@amd.com double MUL_cdb_duty_cycle; 38810234Syasuko.eckert@amd.com double FPU_cdb_duty_cycle; 38910234Syasuko.eckert@amd.com double ROB_reads; 39010234Syasuko.eckert@amd.com double ROB_writes; 39110234Syasuko.eckert@amd.com double total_instructions; 39210234Syasuko.eckert@amd.com double int_instructions; 39310234Syasuko.eckert@amd.com double fp_instructions; 39410234Syasuko.eckert@amd.com double branch_instructions; 39510234Syasuko.eckert@amd.com double branch_mispredictions; 39610234Syasuko.eckert@amd.com double load_instructions; 39710234Syasuko.eckert@amd.com double store_instructions; 39810234Syasuko.eckert@amd.com double committed_instructions; 39910234Syasuko.eckert@amd.com double committed_int_instructions; 40010234Syasuko.eckert@amd.com double committed_fp_instructions; 40110234Syasuko.eckert@amd.com double rename_reads; 40210234Syasuko.eckert@amd.com double rename_writes; 40310234Syasuko.eckert@amd.com double fp_rename_reads; 40410234Syasuko.eckert@amd.com double fp_rename_writes; 40510234Syasuko.eckert@amd.com double inst_window_reads; 40610234Syasuko.eckert@amd.com double inst_window_writes; 40710234Syasuko.eckert@amd.com double inst_window_wakeup_accesses; 40810234Syasuko.eckert@amd.com double fp_inst_window_reads; 40910234Syasuko.eckert@amd.com double fp_inst_window_writes; 41010234Syasuko.eckert@amd.com double fp_inst_window_wakeup_accesses; 41110234Syasuko.eckert@amd.com double int_regfile_reads; 41210234Syasuko.eckert@amd.com double float_regfile_reads; 41310234Syasuko.eckert@amd.com double int_regfile_writes; 41410234Syasuko.eckert@amd.com double float_regfile_writes; 41510234Syasuko.eckert@amd.com double context_switches; 41610234Syasuko.eckert@amd.com double ialu_accesses; 41710234Syasuko.eckert@amd.com double fpu_accesses; 41810234Syasuko.eckert@amd.com double mul_accesses; 41910234Syasuko.eckert@amd.com double cdb_alu_accesses; 42010234Syasuko.eckert@amd.com double cdb_fpu_accesses; 42110234Syasuko.eckert@amd.com double cdb_mul_accesses; 42210234Syasuko.eckert@amd.com double function_calls; 42310152Satgutier@umich.edu}; 42410152Satgutier@umich.edu 42510234Syasuko.eckert@amd.comclass MCParameters { 42610152Satgutier@umich.edupublic: 42710234Syasuko.eckert@amd.com double clockRate; 42810234Syasuko.eckert@amd.com enum MemoryCtrl_type mc_type; 42910234Syasuko.eckert@amd.com double num_mcs; 43010234Syasuko.eckert@amd.com int num_channels; 43110234Syasuko.eckert@amd.com int llcBlockSize; 43210234Syasuko.eckert@amd.com int dataBusWidth; 43310234Syasuko.eckert@amd.com int databus_width; 43410234Syasuko.eckert@amd.com int llc_line_length; 43510234Syasuko.eckert@amd.com int req_window_size_per_channel; 43610234Syasuko.eckert@amd.com int IO_buffer_size_per_channel; 43710234Syasuko.eckert@amd.com int addressbus_width; 43810234Syasuko.eckert@amd.com int opcodeW; 43910234Syasuko.eckert@amd.com int type; 44010234Syasuko.eckert@amd.com bool LVDS; 44110234Syasuko.eckert@amd.com bool withPHY; 44210234Syasuko.eckert@amd.com int peak_transfer_rate; 44310234Syasuko.eckert@amd.com int number_ranks; 44410234Syasuko.eckert@amd.com int reorder_buffer_assoc; 44510234Syasuko.eckert@amd.com int reorder_buffer_nbanks; 44610234Syasuko.eckert@amd.com int read_buffer_assoc; 44710234Syasuko.eckert@amd.com int read_buffer_nbanks; 44810234Syasuko.eckert@amd.com int read_buffer_tag_width; 44910234Syasuko.eckert@amd.com int write_buffer_assoc; 45010234Syasuko.eckert@amd.com int write_buffer_nbanks; 45110234Syasuko.eckert@amd.com int write_buffer_tag_width; 45210152Satgutier@umich.edu}; 45310152Satgutier@umich.edu 45410234Syasuko.eckert@amd.comclass MCStatistics { 45510152Satgutier@umich.edupublic: 45610234Syasuko.eckert@amd.com double duty_cycle; 45710234Syasuko.eckert@amd.com double perc_load; 45810234Syasuko.eckert@amd.com double reads; 45910234Syasuko.eckert@amd.com double writes; 46010152Satgutier@umich.edu}; 46110152Satgutier@umich.edu 46210234Syasuko.eckert@amd.comclass NIUParameters { 46310234Syasuko.eckert@amd.com public: 46410234Syasuko.eckert@amd.com double clockRate; 46510234Syasuko.eckert@amd.com int num_units; 46610234Syasuko.eckert@amd.com int type; 46710234Syasuko.eckert@amd.com}; 46810234Syasuko.eckert@amd.com 46910234Syasuko.eckert@amd.comclass NIUStatistics { 47010234Syasuko.eckert@amd.com public: 47110234Syasuko.eckert@amd.com double duty_cycle; 47210234Syasuko.eckert@amd.com double perc_load; 47310234Syasuko.eckert@amd.com}; 47410234Syasuko.eckert@amd.com 47510234Syasuko.eckert@amd.comclass PCIeParameters { 47610234Syasuko.eckert@amd.com public: 47710234Syasuko.eckert@amd.com double clockRate; 47810234Syasuko.eckert@amd.com int num_channels; 47910234Syasuko.eckert@amd.com int num_units; 48010234Syasuko.eckert@amd.com bool withPHY; 48110234Syasuko.eckert@amd.com int type; 48210234Syasuko.eckert@amd.com}; 48310234Syasuko.eckert@amd.com 48410234Syasuko.eckert@amd.comclass PCIeStatistics { 48510234Syasuko.eckert@amd.com public: 48610234Syasuko.eckert@amd.com double duty_cycle; 48710234Syasuko.eckert@amd.com double perc_load; 48810152Satgutier@umich.edu}; 48910152Satgutier@umich.edu#endif /* BASIC_COMPONENTS_H_ */ 490