Searched refs:MemCmd (Results 1 - 25 of 69) sorted by relevance

123

/gem5/ext/sst/
H A DExtSlave.cc87 ::MemCmd::Command pktCmd = (::MemCmd::Command)pkt->cmd.toInt();
88 assert(pktCmd == ::MemCmd::WriteReq);
102 switch ((::MemCmd::Command)pkt->cmd.toInt()) {
103 case ::MemCmd::HardPFReq:
104 case ::MemCmd::SoftPFReq:
105 case ::MemCmd::LoadLockedReq:
106 case ::MemCmd::ReadExReq:
107 case ::MemCmd::ReadReq: cmd = GetS; break;
108 case ::MemCmd
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H A DExtMaster.cc133 MemCmd::Command cmdO; // command out - gem5
137 case GetS: cmdO = MemCmd::ReadReq; break;
138 case GetX: cmdO = MemCmd::WriteReq; data = true; break;
168 cmdO = MemCmd::LoadLockedReq;
171 cmdO = MemCmd::StoreCondReq;
/gem5/src/cpu/testers/traffic_gen/
H A Dtrace_gen.hh74 MemCmd cmd;
94 return cmd != MemCmd::InvalidCmd;
101 cmd = MemCmd::InvalidCmd;
H A Ddram_rot_gen.cc129 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
H A Dlinear_gen.cc76 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
H A Drandom_gen.cc82 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
H A Ddram_gen.cc141 isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
H A Dbase_gen.cc61 BaseGen::getPacket(Addr addr, unsigned size, const MemCmd& cmd,
H A Dbase_gen.hh81 PacketPtr getPacket(Addr addr, unsigned size, const MemCmd& cmd,
/gem5/src/mem/
H A Dpacket.hh77 class MemCmd class
192 testCmdAttrib(MemCmd::Attribute attrib) const
242 MemCmd(Command _cmd) : cmd(_cmd) { } function in class:MemCmd
243 MemCmd(int _cmd) : cmd((Command)_cmd) { } function in class:MemCmd
244 MemCmd() : cmd(InvalidCmd) { } function in class:MemCmd
246 bool operator==(MemCmd c2) const { return (cmd == c2.cmd); }
247 bool operator!=(MemCmd c2) const { return (cmd != c2.cmd); }
321 typedef MemCmd::Command Command;
324 MemCmd cmd;
553 MemCmd resp_cm
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H A Dport_proxy.cc54 Packet pkt(req, MemCmd::ReadReq);
71 Packet pkt(req, MemCmd::WriteReq);
/gem5/src/mem/cache/
H A Dcache.cc94 assert(pkt->cmd == MemCmd::ReadExReq ||
95 pkt->cmd == MemCmd::SCUpgradeFailReq);
106 pkt->cmd != MemCmd::ReadCleanReq) {
203 if (wbPkt->cmd == MemCmd::CleanEvict) {
209 } else if (wbPkt->cmd == MemCmd::WritebackClean) {
215 assert(wbPkt->cmd == MemCmd::WritebackDirty ||
216 wbPkt->cmd == MemCmd::WriteClean);
243 if (wbPkt->cmd == MemCmd::WritebackDirty ||
244 wbPkt->cmd == MemCmd::WriteClean) {
283 assert(pkt->cmd == MemCmd
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H A Dbase.hh408 inline bool allocOnFill(MemCmd cmd) const
411 cmd == MemCmd::WriteLineReq ||
412 cmd == MemCmd::ReadReq ||
413 cmd == MemCmd::WriteReq ||
923 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
931 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
941 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
948 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
955 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
962 Stats::Formula avgMissLatency[MemCmd
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H A Dnoncoherent_cache.cc88 if (pkt->isWriteback() || pkt->cmd == MemCmd::WriteClean) {
161 PacketPtr pkt = new Packet(cpu_pkt->req, MemCmd::ReadReq, blkSize);
188 assert(pkt->cmd != MemCmd::UpgradeResp);
209 if (!pkt->isWriteback() && pkt->cmd != MemCmd::WriteClean) {
296 assert(tgt_pkt->cmd == MemCmd::HardPFReq);
327 assert(pkt->cmd != MemCmd::UpgradeResp);
H A Dmshr.cc89 if (pkt->isUpgrade() || pkt->cmd == MemCmd::StoreCondReq) {
144 if (pkt->cmd == MemCmd::UpgradeReq) {
145 pkt->cmd = MemCmd::ReadExReq;
147 } else if (pkt->cmd == MemCmd::SCUpgradeReq) {
148 pkt->cmd = MemCmd::SCUpgradeFailReq;
150 } else if (pkt->cmd == MemCmd::StoreCondReq) {
151 pkt->cmd = MemCmd::StoreCondFailReq;
273 Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
331 assert(pkt->cmd != MemCmd::HardPFReq);
505 if (pkt->cmd == MemCmd
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H A Dbase.cc262 if (pkt->cmd == MemCmd::CleanEvict) {
264 } else if (pkt->cmd == MemCmd::WriteClean) {
302 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) {
410 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
460 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp ||
914 if (pkt->cmd == MemCmd::SwapReq) {
1088 assert(pkt->cmd == MemCmd::WritebackDirty);
1107 if (pkt->cmd == MemCmd::WritebackClean &&
1159 if (pkt->cmd == MemCmd::WritebackDirty) {
1185 } else if (pkt->cmd == MemCmd
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/gem5/src/mem/ruby/system/
H A DCacheRecorder.cc91 MemCmd::Command requestType = MemCmd::FlushReq;
116 MemCmd::Command requestType;
119 requestType = MemCmd::ReadReq;
124 requestType = MemCmd::ReadReq;
130 requestType = MemCmd::WriteReq;
/gem5/src/sim/probe/
H A Dmem.hh55 MemCmd cmd;
/gem5/src/cpu/testers/directedtest/
H A DSeriesRequestGenerator.cc68 cmd = MemCmd::WriteReq;
70 cmd = MemCmd::ReadReq;
H A DInvalidateGenerator.cc70 cmd = MemCmd::ReadReq;
75 cmd = MemCmd::WriteReq;
/gem5/src/gpu-compute/
H A Dshader.cc229 Shader::doFunctionalAccess(const RequestPtr &req, MemCmd cmd, void *data,
238 if (cmd == MemCmd::ReadReq) {
240 } else if (cmd == MemCmd::WriteReq) {
243 fatal("unexcepted MemCmd\n");
335 MemCmd cmd, bool suppress_func_errors)
354 AccessMem(address, ptr, size, cu_id, MemCmd::ReadReq, false);
361 AccessMem(address, ptr, size, cu_id, MemCmd::ReadReq, suppress_func_errors);
367 AccessMem(address, ptr, size, cu_id, MemCmd::WriteReq, false);
374 AccessMem(address, ptr, size, cu_id, MemCmd::WriteReq,
H A Dshader.hh172 MemCmd cmd, bool suppress_func_errors);
184 void doFunctionalAccess(const RequestPtr &req, MemCmd cmd, void *data,
/gem5/src/arch/arm/
H A Dstage2_mmu.cc80 Packet pkt = Packet(req, MemCmd::ReadReq);
136 MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
/gem5/src/arch/x86/
H A Dintmessage.hh87 PacketPtr pkt = new Packet(req, MemCmd::MessageReq);
/gem5/src/dev/
H A Ddma_device.hh182 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data,
189 dmaPort.dmaAction(MemCmd::WriteReq, addr, size, event, data, delay);
195 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data,
202 dmaPort.dmaAction(MemCmd::ReadReq, addr, size, event, data, delay);

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