/gem5/src/dev/arm/ |
H A D | base_gic.hh | 118 virtual uint32_t readDistributor(ContextID ctx, Addr daddr) = 0; 119 virtual uint32_t readCpu(ContextID ctx, Addr daddr) = 0; 121 virtual void writeDistributor(ContextID ctx, Addr daddr, 123 virtual void writeCpu(ContextID ctx, Addr daddr, uint32_t data) = 0; 159 * more than one interrupt (one per ContextID). 168 std::unordered_map<ContextID, ArmPPI*> pins; 206 ContextID targetContext() const;
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H A D | gic_v2.hh | 211 BankedRegs& getBankedRegs(ContextID); 218 uint32_t& getIntEnabled(ContextID ctx, uint32_t ix) { 231 uint32_t& getPendingInt(ContextID ctx, uint32_t ix) { 245 uint32_t& getActiveInt(ContextID ctx, uint32_t ix) { 259 uint32_t& getIntGroup(ContextID ctx, uint32_t ix) { 277 uint8_t& getIntPriority(ContextID ctx, uint32_t ix) { 289 uint8_t getIntConfig(ContextID ctx, uint32_t ix) { 301 uint8_t getCpuTarget(ContextID ctx, uint32_t ix) { 325 bool isLevelSensitive(ContextID ctx, uint32_t ix) { 333 bool isGroup0(ContextID ct [all...] |
H A D | base_gic.cc | 105 ContextID cid = tc->contextId(); 140 ContextID
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H A D | gic_v3.hh | 148 getRedistributor(ContextID context_id) const
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H A D | gic_v2.cc | 143 const ContextID ctx = pkt->req->contextId(); 169 GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz) 296 const ContextID ctx = pkt->req->contextId(); 309 GicV2::readCpu(ContextID ctx, Addr daddr) 394 const ContextID ctx = pkt->req->contextId(); 424 GicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data, 563 const ContextID ctx = pkt->req->contextId(); 576 GicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data) 639 GicV2::getBankedRegs(ContextID ctx) { 649 GicV2::softInt(ContextID ct [all...] |
H A D | vgic.cc | 101 ContextID ctx_id = pkt->req->contextId(); 148 ContextID ctx_id = pkt->req->contextId(); 242 ContextID ctx_id = pkt->req->contextId(); 291 ContextID ctx_id = pkt->req->contextId(); 404 VGic::updateIntState(ContextID ctx_id)
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H A D | timer_cpulocal.cc | 97 ContextID cpu_id = pkt->req->contextId(); 175 ContextID cpu_id = pkt->req->contextId();
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/gem5/src/arch/arm/kvm/ |
H A D | gic.hh | 121 uint32_t readDistributor(ContextID ctx, Addr daddr) override; 122 uint32_t readCpu(ContextID ctx, Addr daddr) override; 124 void writeDistributor(ContextID ctx, Addr daddr, 126 void writeCpu(ContextID ctx, Addr daddr, uint32_t data) override; 212 ContextID ctx, Addr daddr); 214 ContextID ctx, Addr daddr);
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H A D | gic.cc | 141 KvmKernelGicV2::readDistributor(ContextID ctx, Addr daddr) 148 KvmKernelGicV2::readCpu(ContextID ctx, Addr daddr) 155 KvmKernelGicV2::writeDistributor(ContextID ctx, Addr daddr, uint32_t data) 162 KvmKernelGicV2::writeCpu(ContextID ctx, Addr daddr, uint32_t data) 288 ContextID ctx, Addr daddr) 297 ContextID ctx, Addr daddr)
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/gem5/src/cpu/ |
H A D | thread_state.hh | 74 ContextID contextId() const { return _contextId; } 76 void setContextId(ContextID id) { _contextId = id; } 169 ContextID _contextId;
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H A D | thread_context.hh | 133 virtual ContextID contextId() const = 0; 135 virtual void setContextId(ContextID id) = 0;
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H A D | thread_context.cc | 124 const ContextID cid1 = one->contextId(); 125 const ContextID cid2 = two->contextId();
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | RubyRequest.hh | 57 ContextID m_contextId; 68 ContextID _proc_id = 100, ContextID _core_id = 99,
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/gem5/src/base/ |
H A D | types.hh | 231 typedef int ContextID; typedef 232 const ContextID InvalidContextID = (ContextID)-1;
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/gem5/src/sim/ |
H A D | system.hh | 203 ThreadContext *getThreadContext(ContextID tid) 595 ContextID registerThreadContext(ThreadContext *tc, 596 ContextID assigned = InvalidContextID); 597 void replaceThreadContext(ThreadContext *tc, ContextID context_id);
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H A D | process.hh | 123 assignThreadContext(ContextID context_id) 166 std::vector<ContextID> contextIds;
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H A D | system.cc | 245 ContextID 246 System::registerThreadContext(ThreadContext *tc, ContextID assigned) 345 System::replaceThreadContext(ThreadContext *tc, ContextID context_id)
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/gem5/src/dev/net/ |
H A D | sinic.hh | 267 void prepareIO(ContextID cpu, int index); 268 void prepareRead(ContextID cpu, int index); 269 void prepareWrite(ContextID cpu, int index); 270 // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result);
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/gem5/src/mem/ |
H A D | request.hh | 383 ContextID _contextId; 410 InstSeqNum seq_num, ContextID cid) 460 MasterID mid, Addr pc, ContextID cid) 472 MasterID mid, Addr pc, ContextID cid, 503 setContext(ContextID context_id) 787 ContextID
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H A D | abstract_mem.hh | 79 const ContextID contextId;
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H A D | physical.cc | 300 vector<ContextID> lal_cid; 377 vector<ContextID> lal_cid;
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/gem5/src/cpu/kvm/ |
H A D | vm.hh | 421 long contextIdToVCpuId(ContextID ctx) const;
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/gem5/src/arch/riscv/ |
H A D | process.cc | 104 for (ContextID ctx: contextIds) 114 for (ContextID ctx: contextIds) {
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/gem5/src/cpu/o3/ |
H A D | thread_context.hh | 110 ContextID contextId() const override { return thread->contextId(); } 112 void setContextId(ContextID id) override { thread->setContextId(id); }
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/gem5/src/cpu/checker/ |
H A D | thread_context.hh | 99 ContextID contextId() const override { return actualTC->contextId(); } 102 setContextId(ContextID id) override
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