Searched defs:misc_reg (Results 1 - 14 of 14) sorted by relevance

/gem5/src/arch/alpha/
H A Disa.cc78 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const argument
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/gem5/src/arch/arm/
H A Disa_device.cc61 DummyISADevice::setMiscReg(int misc_reg, RegVal val) argument
69 DummyISADevice::readMiscReg(int misc_reg) argument
H A Dpmu.cc194 PMU::setMiscReg(int misc_reg, RegVal val) argument
303 PMU::readMiscReg(int misc_reg) argument
312 readMiscRegInt(int misc_reg) argument
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/gem5/src/arch/riscv/
H A Disa.cc112 ISA::readMiscReg(int misc_reg, ThreadContex argument
169 setMiscRegNoEffect(int misc_reg, RegVal val) argument
180 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) argument
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/gem5/src/arch/power/
H A Disa.hh72 readMiscReg(int misc_reg, ThreadContext *tc) argument
79 setMiscRegNoEffect(int misc_reg, RegVal val) argument
85 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) argument
/gem5/src/arch/arm/insts/
H A Dmisc64.cc87 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg, argument
122 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument
143 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument
292 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument
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H A Dmisc64.hh215 MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst, MiscRegIndex misc_reg, bool misc_read, uint32_t _imm, const std::string full_mnem, bool _warning) argument
/gem5/src/arch/mips/
H A Disa.hh90 void updateCP0ReadView(int misc_reg, ThreadID tid) { } argument
H A Disa.cc421 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const argument
435 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) argument
448 setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument
461 setRegMask(int misc_reg, RegVal val, ThreadID tid) argument
476 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) argument
499 filterCP0Write(int misc_reg, int reg_sel, RegVal val) argument
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/gem5/src/cpu/minor/
H A Ddyn_inst.cc146 RegIndex misc_reg = reg.index(); local
153 os << 'n' << misc_reg; local
/gem5/src/cpu/o3/
H A Dthread_context_impl.hh346 O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val) argument
355 O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val) argument
H A Dcpu.cc1169 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const argument
1176 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) argument
1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument
1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) argument
/gem5/src/cpu/checker/
H A Dcpu.hh467 setMiscRegNoEffect(int misc_reg, RegVal val) argument
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/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc114 Gicv3CPUInterface::readMiscReg(int misc_reg) argument
734 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) argument
1624 setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const argument
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