| /gem5/src/arch/alpha/ |
| H A D | isa.cc | 78 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const argument
[all...] |
| /gem5/src/arch/arm/ |
| H A D | isa_device.cc | 61 DummyISADevice::setMiscReg(int misc_reg, RegVal val) argument
69 DummyISADevice::readMiscReg(int misc_reg) argument
|
| H A D | pmu.cc | 194 PMU::setMiscReg(int misc_reg, RegVal val) argument
303 PMU::readMiscReg(int misc_reg) argument
312 readMiscRegInt(int misc_reg) argument
[all...] |
| /gem5/src/arch/riscv/ |
| H A D | isa.cc | 112 ISA::readMiscReg(int misc_reg, ThreadContex argument
169 setMiscRegNoEffect(int misc_reg, RegVal val) argument
180 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) argument
[all...] |
| /gem5/src/arch/power/ |
| H A D | isa.hh | 72 readMiscReg(int misc_reg, ThreadContext *tc) argument
79 setMiscRegNoEffect(int misc_reg, RegVal val) argument
85 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) argument
|
| /gem5/src/arch/arm/insts/ |
| H A D | misc64.cc | 87 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg, argument
122 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument
143 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument
292 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument
[all...] |
| H A D | misc64.hh | 215 MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst, MiscRegIndex misc_reg, bool misc_read, uint32_t _imm, const std::string full_mnem, bool _warning) argument
|
| /gem5/src/arch/mips/ |
| H A D | isa.hh | 90 void updateCP0ReadView(int misc_reg, ThreadID tid) { } argument
|
| H A D | isa.cc | 421 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const argument
435 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) argument
448 setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument
461 setRegMask(int misc_reg, RegVal val, ThreadID tid) argument
476 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) argument
499 filterCP0Write(int misc_reg, int reg_sel, RegVal val) argument
[all...] |
| /gem5/src/cpu/minor/ |
| H A D | dyn_inst.cc | 146 RegIndex misc_reg = reg.index(); local
153 os << 'n' << misc_reg; local
|
| /gem5/src/cpu/o3/ |
| H A D | thread_context_impl.hh | 346 O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val) argument
355 O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val) argument
|
| H A D | cpu.cc | 1169 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const argument
1176 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid) argument
1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument
1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) argument
|
| /gem5/src/cpu/checker/ |
| H A D | cpu.hh | 467 setMiscRegNoEffect(int misc_reg, RegVal val) argument
[all...] |
| /gem5/src/dev/arm/ |
| H A D | gic_v3_cpu_interface.cc | 114 Gicv3CPUInterface::readMiscReg(int misc_reg) argument
734 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) argument
1624 setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const argument
[all...] |