Lines Matching defs:misc_reg
114 Gicv3CPUInterface::readMiscReg(int misc_reg)
116 RegVal value = isa->readMiscRegNoEffect(misc_reg);
120 switch (misc_reg) {
725 misc_reg, miscRegName[misc_reg]);
729 miscRegName[misc_reg], value);
734 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
738 miscRegName[misc_reg], val);
742 switch (misc_reg) {
1097 misc_reg == MISCREG_ICV_BPR0_EL1 ? Gicv3::G0S : Gicv3::G1NS;
1455 ICH_LRC ich_lrc = isa->readMiscRegNoEffect(misc_reg);
1491 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1500 ICH_LR_EL2 ich_lr_el2 = isa->readMiscRegNoEffect(misc_reg);
1606 misc_reg, miscRegName[misc_reg]);
1609 isa->setMiscRegNoEffect(misc_reg, val);
1617 Gicv3CPUInterface::readBankedMiscReg(MiscRegIndex misc_reg) const
1620 isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()));
1624 Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const
1627 isa->snsBankedIndex64(misc_reg, !isSecureBelowEL3()), val);