arch/mips/isa.cc

421 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
423     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
426             misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
427             miscRegFile[misc_reg][reg_sel]);
428     return miscRegFile[misc_reg][reg_sel];
435 ISA::readMiscReg(int misc_reg, ThreadContext *tc,  ThreadID tid)
437     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
441             misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
442             miscRegFile[misc_reg][reg_sel]);
444     return miscRegFile[misc_reg][reg_sel];
448 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
450     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
455             tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
457     miscRegFile[misc_reg][reg_sel] = val;
461 ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid)
463     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
467             tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
468     miscRegFile_WriteMask[misc_reg][reg_sel] = val;
476 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
478     int reg_sel = (bankType[misc_reg] == perThreadContext)
484             tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
486     RegVal cp0_val = filterCP0Write(misc_reg, reg_sel, val);
488     miscRegFile[misc_reg][reg_sel] = cp0_val;
499 ISA::filterCP0Write(int misc_reg, int reg_sel, RegVal val)
504     retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
505     RegVal curVal = miscRegFile[misc_reg][reg_sel];
507     curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
512             miscRegFile_WriteMask[misc_reg][reg_sel],
513             ~miscRegFile_WriteMask[misc_reg][reg_sel],
514             val, miscRegFile[misc_reg][reg_sel], retVal);