Searched refs:seq_num (Results 1 - 21 of 21) sorted by relevance

/gem5/src/cpu/pred/
H A Dindirect.hh54 InstSeqNum seq_num, ThreadID tid) = 0;
55 virtual void commit(InstSeqNum seq_num, ThreadID tid,
57 virtual void squash(InstSeqNum seq_num, ThreadID tid) = 0;
58 virtual void recordTarget(InstSeqNum seq_num, void * indirect_history,
H A Dsimple_indirect.hh48 void recordIndirect(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num,
50 void commit(InstSeqNum seq_num, ThreadID tid, void * indirect_history);
51 void squash(InstSeqNum seq_num, ThreadID tid);
52 void recordTarget(InstSeqNum seq_num, void * indirect_history,
85 HistoryEntry(Addr br_addr, Addr tgt_addr, InstSeqNum seq_num) argument
86 : pcAddr(br_addr), targetAddr(tgt_addr), seqNum(seq_num) { }
H A Dsimple_indirect.cc115 InstSeqNum seq_num, ThreadID tid)
117 DPRINTF(Indirect, "Recording %x seq:%d\n", br_addr, seq_num);
118 HistoryEntry entry(br_addr, tgt_addr, seq_num);
123 SimpleIndirectPredictor::commit(InstSeqNum seq_num, ThreadID tid,
126 DPRINTF(Indirect, "Committing seq:%d\n", seq_num);
136 t_info.pathHist[t_info.headHistEntry].seqNum <= seq_num) {
146 SimpleIndirectPredictor::squash(InstSeqNum seq_num, ThreadID tid)
148 DPRINTF(Indirect, "Squashing seq:%d\n", seq_num);
152 if (squash_itr->seqNum > seq_num) {
176 InstSeqNum seq_num, voi
[all...]
H A Dbpred_unit.hh204 PredictorHistory(const InstSeqNum &seq_num, Addr instPC, argument
208 : seqNum(seq_num), pc(instPC), bpHistory(bp_history),
/gem5/util/
H A Dencode_inst_dep_trace.py80 # seq_num,[pc],[weight,]type,[p_addr,size,flags,]comp_delay:[rob_dep]:
155 dep_record.seq_num = long(inst_info_list[0])
162 print "Seq. num", dep_record.seq_num, "has unsupported type", \
167 print "Seq. num", dep_record.seq_num, "is of INVALID type"
H A Ddecode_inst_dep_trace.py80 # seq_num,[pc],[weight,]type,[p_addr,size,flags,]comp_delay:[rob_dep]:
161 ascii_out.write('%s' % (packet.seq_num))
176 print "Seq. num", packet.seq_num, "has unsupported type", \
/gem5/src/cpu/o3/
H A Dmem_dep_unit.hh56 size_t operator() (const InstSeqNum &seq_num) const {
57 unsigned a = (unsigned)seq_num;
H A Ddyn_inst_impl.hh55 InstSeqNum seq_num, O3CPU *cpu)
56 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
52 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu) argument
H A Dfetch.hh340 const InstSeqNum seq_num, ThreadID tid);
354 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
H A Ddyn_inst.hh83 InstSeqNum seq_num, O3CPU *cpu);
H A Dcpu.cc1595 FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid) argument
1607 tid, seq_num, (*inst_iter)->seqNum);
1609 while ((*inst_iter)->seqNum > seq_num) {
H A Dfetch_impl.hh815 const InstSeqNum seq_num, ThreadID tid)
823 cpu->removeInstsUntil(seq_num, tid);
884 const InstSeqNum seq_num, DynInstPtr squashInst,
813 squashFromDecode(const TheISA::PCState &newPC, const DynInstPtr squashInst, const InstSeqNum seq_num, ThreadID tid) argument
883 squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, DynInstPtr squashInst, ThreadID tid) argument
H A Dcpu.hh521 void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
/gem5/src/cpu/
H A Dbase_dyn_inst_impl.hh65 InstSeqNum seq_num, ImplCPU *cpu)
74 seqNum = seq_num;
62 BaseDynInst(const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop, TheISA::PCState _pc, TheISA::PCState _predPC, InstSeqNum seq_num, ImplCPU *cpu) argument
H A Dbase_dyn_inst.hh417 * @param seq_num The sequence number of the instruction.
422 InstSeqNum seq_num, ImplCPU *cpu);
/gem5/src/cpu/o3/probe/
H A Delastic_trace.cc231 InstSeqNum seq_num = dyn_inst->seqNum; local
239 tempStore[seq_num] = exec_info_ptr;
253 " %i (%s)\n", seq_num,
263 if (seq_num - last_writer < depWindowSize) {
286 " %i (%s)\n", seq_num, phys_dest_reg->flatIndex(),
288 physRegDepMap[phys_dest_reg->flatIndex()] = seq_num;
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.hh114 uint64_t seq_num; member in struct:Trace::TarmacParserRecord::ParserInstEntry
H A Dtarmac_parser.cc751 << "[seq_num: " << dec << instRecord.seq_num
908 instRecord.seq_num = atoi(&buf[1]);
928 warn("Invalid TARMAC trace record (seq_num: %lld)",
929 instRecord.seq_num);
/gem5/src/mem/
H A Drequest.hh410 InstSeqNum seq_num, ContextID cid)
414 _reqInstSeqNum(seq_num), atomicOpFunctor(nullptr), translateDelta(0),
873 setReqInstSeqNum(const InstSeqNum seq_num) argument
876 _reqInstSeqNum = seq_num;
409 Request(Addr paddr, unsigned size, Flags flags, MasterID mid, InstSeqNum seq_num, ContextID cid) argument
/gem5/src/cpu/trace/
H A Dtrace_cpu.cc806 TraceCPU::ElasticDataGen::addToSortedReadyList(NodeSeqNum seq_num, argument
810 ready_node.seqNum = seq_num;
845 if (seq_num < itr->seqNum)
1293 element->seqNum = pkt_msg.seq_num();
H A Dtrace_cpu.hh948 * @param seq_num seq. num of ready node
951 void addToSortedReadyList(NodeSeqNum seq_num, Tick exec_tick);

Completed in 57 milliseconds