/gem5/src/arch/sparc/ |
H A D | remote_gdb.cc | 179 PCState pc = context->pcState(); local 180 r.pc = htobe((uint32_t)pc.pc()); 181 r.npc = htobe((uint32_t)pc.npc()); 195 PCState pc = context->pcState(); local 196 r.pc = htobe(pc.pc()); 197 r.npc = htobe(pc 213 PCState pc; local 229 PCState pc; local [all...] |
/gem5/src/arch/arm/tracers/ |
H A D | tarmac_base.cc | 64 PCState pc, 68 addr(pc.instAddr()) , 71 isetstate(pcToISetState(pc)), 85 TarmacBaseRecord::RegEntry::RegEntry(PCState pc) argument 86 : isetstate(pcToISetState(pc)) 99 TarmacBaseRecord::pcToISetState(PCState pc) argument 103 if (pc.aarch64()) 105 else if (!pc.thumb() && !pc.jazelle()) 107 else if (pc 62 InstEntry( ThreadContext* thread, PCState pc, const StaticInstPtr staticInst, bool predicate) argument [all...] |
H A D | tarmac_tracer.hh | 67 : thread(_thread), staticInst(_staticInst), pc(_pc) 75 ArmISA::PCState pc; member in class:Trace::TarmacContext 102 ArmISA::PCState pc,
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/gem5/src/dev/x86/ |
H A D | south_bridge.cc | 35 #include "dev/x86/pc.hh" 44 Pc * pc = dynamic_cast<Pc *>(platform); local 45 assert(pc); 46 pc->southBridge = this;
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/gem5/src/systemc/tests/systemc/misc/sim_tests/simple_cpu/ |
H A D | simple_cpu.cpp | 50 unsigned pc; // Program counter local 65 pc = 0x000000; // Power up reset value 86 program_counter.write(pc); 108 printf("\tPC = 0x%x\n", pc); 111 // Don't write pc and execution will stop 118 pc = pc + 1; 119 program_counter.write(pc); 126 pc = pc 232 unsigned pc, instr; local 241 sc_signal<unsigned> pc; local [all...] |
/gem5/src/cpu/ |
H A D | pc_event.hh | 52 PCEvent(PCEventQueue *q, const std::string &desc, Addr pc); 60 Addr pc() const { return evpc; } function in class:PCEvent 73 return l->pc() < r->pc(); 75 bool operator()(const record_t &l, Addr pc) const { 76 return l->pc() < pc; 78 bool operator()(Addr pc, const record_t &r) const { argument 79 return pc < r->pc(); 119 PCEvent(PCEventQueue *q, const std::string &desc, Addr pc) argument [all...] |
H A D | pc_event.cc | 64 event->pc(), event->descr()); 83 event->pc(), event->descr()); 93 Addr pc = tc->instAddr(); local 95 range_t range = equal_range(pc); 97 // Make sure that the pc wasn't changed as the side effect of 101 if (pc != tc->instAddr()) 105 (*i)->pc(), (*i)->descr()); 121 cprintf("%d: event at %#x: %s\n", curTick(), (*i)->pc(), 126 PCEventQueue::equal_range(Addr pc) argument 128 return std::equal_range(pc_map.begin(), pc_map.end(), pc, MapCompar 163 PanicPCEvent(PCEventQueue *q, const std::string &desc, Addr pc) argument [all...] |
H A D | static_inst.cc | 61 generateDisassembly(Addr pc, const SymbolTable *symtab) const override 83 StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, argument 87 tgt = branchTarget(pc); 107 StaticInst::branchTarget(const TheISA::PCState &pc) const 123 StaticInst::disassemble(Addr pc, const SymbolTable *symtab) const argument 126 cachedDisassembly = new string(generateDisassembly(pc, symtab));
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/gem5/src/arch/arm/insts/ |
H A D | branch64.cc | 49 pcs.instNPC(pcs.pc() + imm); 58 pcs.instNPC(pcs.pc() + imm); 67 pcs.instNPC(pcs.pc() + imm2); 74 Addr pc, const SymbolTable *symtab) const 78 printTarget(ss, pc + imm, symtab); 84 Addr pc, const SymbolTable *symtab) const 88 printTarget(ss, pc + imm, symtab); 94 Addr pc, const SymbolTable *symtab) const 104 Addr pc, const SymbolTable *symtab) const 115 Addr pc, cons 73 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument 83 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument 93 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument 103 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument 114 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument 123 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument 135 generateDisassembly( Addr pc, const SymbolTable *symtab) const argument [all...] |
H A D | branch.cc | 47 BranchReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 56 BranchImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 60 printTarget(ss, pc + imm, symtab); 65 BranchRegReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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/gem5/src/arch/power/insts/ |
H A D | branch.cc | 39 PCDependentDisassembly::disassemble(Addr pc, const SymbolTable *symtab) const argument 42 pc != cachedPC || symtab != cachedSymtab) 48 new std::string(generateDisassembly(pc, symtab)); 49 cachedPC = pc; 57 BranchPCRel::branchTarget(const PowerISA::PCState &pc) const 59 return (uint32_t)(pc.pc() + disp); 63 BranchPCRel::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 69 Addr target = pc + disp; 81 BranchNonPCRel::branchTarget(const PowerISA::PCState &pc) cons 87 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 109 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 135 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 161 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument [all...] |
H A D | condition.cc | 36 CondLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 49 CondMoveOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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/gem5/src/arch/generic/ |
H A D | types.hh | 148 Addr pc() const { return _pc; } function in class:GenericISA::SimplePCState 149 void pc(Addr val) { _pc = val; } function in class:GenericISA::SimplePCState 157 pc(val); 173 return this->npc() != this->pc() + sizeof(MachInst); 187 operator<<(std::ostream & os, const SimplePCState<MachInst> &pc) argument 189 ccprintf(os, "(%#x=>%#x)", pc.pc(), pc.npc()); 231 return this->npc() != this->pc() + sizeof(MachInst) || 243 // End the macroop by resetting the upc and advancing the regular pc 285 operator <<(std::ostream & os, const UPCState<MachInst> &pc) argument 364 operator <<(std::ostream & os, const DelaySlotPCState<MachInst> &pc) argument 463 operator <<(std::ostream & os, const DelaySlotUPCState<MachInst> &pc) argument [all...] |
/gem5/src/arch/sparc/insts/ |
H A D | micro.cc | 37 SparcMacroInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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H A D | mem.hh | 55 Addr pc, const SymbolTable *symtab) const override; 71 Addr pc, const SymbolTable *symtab) const override;
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H A D | trap.hh | 60 Addr pc, const SymbolTable *symtab) const override; 71 generateDisassembly(Addr pc, const SymbolTable *symtab) const override
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H A D | integer.cc | 44 IntOp::printPseudoOps(std::ostream &os, Addr pc, argument 58 IntOpImm::printPseudoOps(std::ostream &os, Addr pc, argument 83 IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 87 if (printPseudoOps(response, pc, symtab)) 98 IntOpImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 102 if (printPseudoOps(response, pc, symtab)) 116 SetHi::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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H A D | integer.hh | 55 Addr pc, const SymbolTable *symtab) const override; 57 virtual bool printPseudoOps(std::ostream &os, Addr pc, 76 Addr pc, const SymbolTable *symtab) const override; 78 bool printPseudoOps(std::ostream &os, Addr pc, 128 Addr pc, const SymbolTable *symtab) const override;
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/gem5/src/arch/riscv/insts/ |
H A D | compressed.hh | 52 Addr pc, const SymbolTable *symtab) const override;
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H A D | mem.cc | 48 Load::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument 57 Store::generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
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H A D | amo.hh | 56 Addr pc, const SymbolTable *symtab) const override; 66 Addr pc, const SymbolTable *symtab) const override; 76 Addr pc, const SymbolTable *symtab) const override; 86 Addr pc, const SymbolTable *symtab) const override; 96 Addr pc, const SymbolTable *symtab) const override; 106 Addr pc, const SymbolTable *symtab) const override; 116 Addr pc, const SymbolTable *symtab) const override;
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H A D | amo.cc | 47 string MemFenceMicro::generateDisassembly(Addr pc, argument 62 string LoadReserved::generateDisassembly(Addr pc, argument 71 string LoadReservedMicro::generateDisassembly(Addr pc, argument 81 string StoreCond::generateDisassembly(Addr pc, argument 91 string StoreCondMicro::generateDisassembly(Addr pc, argument 102 string AtomicMemOp::generateDisassembly(Addr pc, argument 112 string AtomicMemOpMicro::generateDisassembly(Addr pc, argument
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H A D | standard.hh | 54 Addr pc, const SymbolTable *symtab) const override; 80 generateDisassembly(Addr pc, const SymbolTable *symtab) const override 102 Addr pc, const SymbolTable *symtab) const override;
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/gem5/src/arch/arm/ |
H A D | decoder.cc | 155 Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) argument 158 offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC; 159 emi.thumb = pc.thumb(); 160 emi.aarch64 = pc.aarch64(); 165 const Addr alignment(pc.thumb() ? 0x1 : 0x3); 167 pc.instAddr() & alignment ? DecoderFault::UNALIGNED : DecoderFault::OK); 174 Decoder::decode(ArmISA::PCState &pc) argument 182 pc.npc(pc [all...] |
/gem5/src/arch/alpha/ |
H A D | decoder.hh | 67 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) argument 72 ext_inst |= (static_cast<ExtMachInst>(pc.pc() & 0x1) << 32);
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