/gem5/src/cpu/o3/ |
H A D | regfile.cc | 138 int reg_idx = 0; local 141 for (reg_idx = 0; reg_idx < numPhysicalIntRegs; reg_idx++) { 142 assert(intRegIds[reg_idx].index() == reg_idx); 148 for (reg_idx = 0; reg_idx < numPhysicalFloatRegs; reg_idx++) { 149 assert(floatRegIds[reg_idx] [all...] |
H A D | thread_context_impl.hh | 208 O3ThreadContext<Impl>::readIntRegFlat(RegIndex reg_idx) const 210 return cpu->readArchIntReg(reg_idx, thread->threadId()); 215 O3ThreadContext<Impl>::readFloatRegFlat(RegIndex reg_idx) const 217 return cpu->readArchFloatReg(reg_idx, thread->threadId()); 258 O3ThreadContext<Impl>::readCCRegFlat(RegIndex reg_idx) const 260 return cpu->readArchCCReg(reg_idx, thread->threadId()); 265 O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val) argument 267 cpu->setArchIntReg(reg_idx, val, thread->threadId()); 274 O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val) argument 276 cpu->setArchFloatReg(reg_idx, va 283 setVecRegFlat( RegIndex reg_idx, const VecRegContainer& val) argument 302 setVecPredRegFlat(RegIndex reg_idx, const VecPredRegContainer& val) argument 312 setCCRegFlat(RegIndex reg_idx, RegVal val) argument [all...] |
H A D | cpu.hh | 359 const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const; 364 VecRegContainer& getWritableVecReg(PhysRegIdPtr reg_idx); 404 const VecElem& readVecElem(PhysRegIdPtr reg_idx) const; 406 const VecPredRegContainer& readVecPredReg(PhysRegIdPtr reg_idx) const; 408 VecPredRegContainer& getWritableVecPredReg(PhysRegIdPtr reg_idx); 416 void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val); 418 void setVecElem(PhysRegIdPtr reg_idx, const VecElem& val); 420 void setVecPredReg(PhysRegIdPtr reg_idx, const VecPredRegContainer& val); 424 RegVal readArchIntReg(int reg_idx, ThreadID tid); 426 RegVal readArchFloatReg(int reg_idx, ThreadI 435 readArchVecLane(int reg_idx, int lId, ThreadID tid) const argument 446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) argument [all...] |
H A D | thread_context.hh | 191 readReg(RegIndex reg_idx) argument 194 reg_idx)).index()); 197 readIntReg(RegIndex reg_idx) const override 200 reg_idx)).index()); 204 readFloatReg(RegIndex reg_idx) const override 207 reg_idx)).index()); 305 readCCReg(RegIndex reg_idx) const override 308 reg_idx)).index()); 313 setIntReg(RegIndex reg_idx, RegVal val) override 315 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)) [all...] |
H A D | cpu.cc | 1316 FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) argument 1320 RegId(IntRegClass, reg_idx)); 1327 FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) argument 1331 RegId(FloatRegClass, reg_idx)); 1338 FullO3CPU<Impl>::readArchVecReg(int reg_idx, ThreadID tid) const 1342 RegId(VecRegClass, reg_idx)); 1348 FullO3CPU<Impl>::getWritableArchVecReg(int reg_idx, ThreadID tid) 1352 RegId(VecRegClass, reg_idx)); 1358 FullO3CPU<Impl>::readArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, 1362 RegId(VecElemClass, reg_idx, ld 1388 readArchCCReg(int reg_idx, ThreadID tid) argument 1399 setArchIntReg(int reg_idx, RegVal val, ThreadID tid) argument 1410 setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) argument 1421 setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid) argument 1431 setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, const VecElem& val, ThreadID tid) argument 1441 setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, ThreadID tid) argument 1451 setArchCCReg(int reg_idx, RegVal val, ThreadID tid) argument [all...] |
H A D | regfile.hh | 179 PhysRegIdPtr getMiscRegId(RegIndex reg_idx) { argument 180 return &miscRegIds[reg_idx];
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H A D | dyn_inst.hh | 411 int reg_idx = idx; variable 412 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
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/gem5/src/arch/x86/insts/ |
H A D | static_inst.cc | 135 RegIndex reg_idx = reg.index(); local 139 bool fold = reg_idx & IntFoldBit; 140 reg_idx &= ~IntFoldBit; 144 else if (reg_idx < 8 && size == 1) 147 switch (reg_idx) { 197 ccprintf(os, microFormats[size], reg_idx - NUM_INTREGS); 202 if (reg_idx < NumMMXRegs) { 203 ccprintf(os, "%%mmx%d", reg_idx); 206 reg_idx -= NumMMXRegs; 207 if (reg_idx < NumXMMReg [all...] |
/gem5/src/arch/sparc/insts/ |
H A D | static_inst.cc | 104 RegIndex reg_idx = reg.index(); local 108 while (reg_idx >= MaxMicroReg) 109 reg_idx -= MaxMicroReg; 110 if (reg_idx == FramePointerReg) 112 else if (reg_idx == StackPointerReg) 114 else if (reg_idx < MaxGlobal) 115 ccprintf(os, "%%g%d", reg_idx); 116 else if (reg_idx < MaxOutput) 117 ccprintf(os, "%%o%d", reg_idx - MaxGlobal); 118 else if (reg_idx < MaxLoca [all...] |
/gem5/src/cpu/checker/ |
H A D | thread_context.hh | 239 readIntReg(RegIndex reg_idx) const override 241 return actualTC->readIntReg(reg_idx); 245 readFloatReg(RegIndex reg_idx) const override 247 return actualTC->readFloatReg(reg_idx); 341 readCCReg(RegIndex reg_idx) const override 343 return actualTC->readCCReg(reg_idx); 347 setIntReg(RegIndex reg_idx, RegVal val) override 349 actualTC->setIntReg(reg_idx, val); 350 checkerTC->setIntReg(reg_idx, val); 354 setFloatReg(RegIndex reg_idx, RegVa [all...] |
/gem5/src/cpu/ |
H A D | simple_thread.hh | 285 readIntReg(RegIndex reg_idx) const override 287 int flatIndex = isa->flattenIntIndex(reg_idx); 291 reg_idx, flatIndex, regVal); 296 readFloatReg(RegIndex reg_idx) const override 298 int flatIndex = isa->flattenFloatIndex(reg_idx); 302 reg_idx, flatIndex, regVal); 442 readCCReg(RegIndex reg_idx) const override 445 int flatIndex = isa->flattenCCIndex(reg_idx); 450 reg_idx, flatIndex, regVal); 459 setIntReg(RegIndex reg_idx, RegVa [all...] |
H A D | thread_context.hh | 209 virtual RegVal readIntReg(RegIndex reg_idx) const = 0; 211 virtual RegVal readFloatReg(RegIndex reg_idx) const = 0; 251 virtual RegVal readCCReg(RegIndex reg_idx) const = 0; 253 virtual void setIntReg(RegIndex reg_idx, RegVal val) = 0; 255 virtual void setFloatReg(RegIndex reg_idx, RegVal val) = 0; 264 virtual void setCCReg(RegIndex reg_idx, RegVal val) = 0;
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H A D | reg_class.hh | 93 RegId(RegClass reg_class, RegIndex reg_idx) argument 94 : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {} 96 explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx) argument 97 : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
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/gem5/src/arch/arm/insts/ |
H A D | static_inst.cc | 296 ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx, argument 302 if (reg_idx == INTREG_UREG0) 304 else if (reg_idx == INTREG_SPX) 306 else if (reg_idx == INTREG_X31) 309 ccprintf(os, "%s%d", (opWidth == 32) ? "w" : "x", reg_idx); 311 switch (reg_idx) { 325 ccprintf(os, "r%d", reg_idx); 342 ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const 344 ccprintf(os, "f%d", reg_idx); 348 ArmStaticInst::printVecReg(std::ostream &os, RegIndex reg_idx, argument [all...] |
H A D | static_inst.hh | 159 void printIntReg(std::ostream &os, RegIndex reg_idx, 161 void printFloatReg(std::ostream &os, RegIndex reg_idx) const; 162 void printVecReg(std::ostream &os, RegIndex reg_idx, 164 void printVecPredReg(std::ostream &os, RegIndex reg_idx) const; 165 void printCCReg(std::ostream &os, RegIndex reg_idx) const; 166 void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
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H A D | macromem.cc | 147 unsigned reg_idx; local 150 reg_idx = force_user ? intRegInMode(MODE_USER, reg) : reg; 153 if (writeback && reg_idx == INTREG_PC) { 159 } else if (reg_idx == INTREG_PC && exception_ret) { 161 *uop = new MicroLdrRetUop(machInst, reg_idx, 165 *uop = new MicroLdrUop(machInst, reg_idx, 170 if (!writeback && reg_idx == INTREG_PC) { 180 *uop = new MicroStrUop(machInst, reg_idx, rn, up, addr);
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/gem5/src/cpu/kvm/ |
H A D | x86_cpu.cc | 291 const unsigned reg_idx((i + top) & 0x7); 292 const bool empty(!((fpu.ftwx >> reg_idx) & 0x1)); 297 inform("\t\tST%i/%i: 0x%s (%f)%s\n", i, reg_idx, 839 const unsigned reg_idx((i + top) & 0x7); 841 tc->readFloatReg(FLOATREG_FPR(reg_idx)))); 843 reg_idx, i, value); 1049 const unsigned reg_idx((i + top) & 0x7); 1052 reg_idx, i, value); 1053 tc->setFloatReg(FLOATREG_FPR(reg_idx), floatToBits64(value));
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