/gem5/src/dev/arm/ |
H A D | smmu_v3_ptops.cc | 46 V7LPageTableOps::isValid(pte_t pte, unsigned level) const argument 49 case 1: return pte & 0x1; 50 case 2: return pte & 0x1; 51 case 3: return (pte & 0x1) && (pte & 0x2); 57 V7LPageTableOps::isLeaf(pte_t pte, unsigned level) const argument 60 case 1: return !(pte & 0x2); 61 case 2: return !(pte & 0x2); 68 V7LPageTableOps::isWritable(pte_t pte, unsigned level, bool stage2) const argument 70 return stage2 ? bits(pte, 74 nextLevelPointer(pte_t pte, unsigned level) const argument 103 pageMask(pte_t pte, unsigned level) const argument 137 isValid(pte_t pte, unsigned level) const argument 149 isLeaf(pte_t pte, unsigned level) const argument 161 isWritable(pte_t pte, unsigned level, bool stage2) const argument 167 nextLevelPointer(pte_t pte, unsigned level) const argument 195 pageMask(pte_t pte, unsigned level) const argument 235 isValid(pte_t pte, unsigned level) const argument 247 isLeaf(pte_t pte, unsigned level) const argument 259 isWritable(pte_t pte, unsigned level, bool stage2) const argument 265 nextLevelPointer(pte_t pte, unsigned level) const argument 293 pageMask(pte_t pte, unsigned level) const argument 336 isValid(pte_t pte, unsigned level) const argument 347 isLeaf(pte_t pte, unsigned level) const argument 358 isWritable(pte_t pte, unsigned level, bool stage2) const argument 364 nextLevelPointer(pte_t pte, unsigned level) const argument 390 pageMask(pte_t pte, unsigned level) const argument [all...] |
H A D | smmu_v3_ptops.hh | 51 virtual bool isValid(pte_t pte, unsigned level) const = 0; 52 virtual bool isLeaf(pte_t pte, unsigned level) const = 0; 53 virtual bool isWritable(pte_t pte, unsigned level, bool stage2) const = 0; 54 virtual Addr nextLevelPointer(pte_t pte, unsigned level) const = 0; 56 virtual Addr pageMask(pte_t pte, unsigned level) const = 0; 64 bool isValid(pte_t pte, unsigned level) const override; 65 bool isLeaf(pte_t pte, unsigned level) const override; 66 bool isWritable(pte_t pte, unsigned level, bool stage2) const override; 67 Addr nextLevelPointer(pte_t pte, unsigned level) const override; 69 Addr pageMask(pte_t pte, unsigne [all...] |
H A D | smmu_v3_transl.cc | 733 PageTableOps::pte_t pte = 0; local 745 doReadPTE(yield, addr, pte_addr, &pte, 1, level); 748 level, pte, pte_addr); 754 bool valid = pt_ops->isValid(pte, level); 755 bool leaf = pt_ops->isLeaf(pte, level); 766 !pt_ops->isWritable(pte, level, false)) 775 walkPtr = pt_ops->nextLevelPointer(pte, level); 794 tr.addrMask = pt_ops->pageMask(pte, level); 796 tr.writable = pt_ops->isWritable(pte, level, false); 817 PageTableOps::pte_t pte; local [all...] |
/gem5/src/arch/x86/ |
H A D | pagetable_walker.cc | 286 PageTableEntry pte; local 288 pte = read->getLE<uint64_t>(); 290 pte = read->getLE<uint32_t>(); 292 bool uncacheable = pte.pcd; 297 bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX; 301 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte); 302 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * dataSize; 303 doWrite = !pte.a; 304 pte.a = 1; 305 entry.writable = pte [all...] |
H A D | pagetable.hh | 159 Addr paddr() { return pte.base << PageShift; } 160 void paddr(Addr addr) { pte.base = addr >> PageShift; } 162 bool present() { return pte.p; } 163 void present(bool p) { pte.p = p ? 1 : 0; } 165 bool uncacheable() { return pte.pcd; } 166 void uncacheable(bool u) { pte.pcd = u ? 1 : 0; } 168 bool readonly() { return !pte.w; } 169 void readonly(bool r) { pte.w = r ? 0 : 1; } 176 pte = p.read<PageTableEntry>(entryAddr); 183 pte 200 PageTableEntry pte; member in class:X86ISA::LongModePTE [all...] |
H A D | tlb.cc | 362 const EmulationPageTable::Entry *pte = local 364 if (!pte && mode != Execute) { 368 pte = p->pTable->lookup(vaddr); 371 if (!pte) { 377 pte->paddr); 379 p->pTable->pid(), alignedVaddr, pte->paddr, 380 pte->flags & EmulationPageTable::Uncacheable, 381 pte->flags & EmulationPageTable::ReadOnly));
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/gem5/src/arch/mips/ |
H A D | tlb.cc | 87 PTE *pte = &table[index]; local 90 Addr Mask = pte->Mask; 92 Addr VPN = pte->VPN; 94 (pte->G || (asn == pte->asid))) { 96 retval = pte; 125 PTE *pte = &table[index]; local 128 Addr Mask = pte->Mask; 130 Addr VPN = pte->VPN; 132 (pte [all...] |
H A D | tlb.hh | 96 void insert(Addr vaddr, MipsISA::PTE &pte); 97 void insertAt(MipsISA::PTE &pte, unsigned Index, int _smallPages);
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/gem5/src/arch/riscv/ |
H A D | tlb.cc | 89 PTE *pte = &table[index]; local 92 Addr Mask = pte->Mask; 94 Addr VPN = pte->VPN; 96 (pte->G || (asn == pte->asid))) { 98 retval = pte; 127 PTE *pte = &table[index]; local 130 Addr Mask = pte->Mask; 132 Addr VPN = pte->VPN; 134 (pte [all...] |
H A D | tlb.hh | 95 void insert(Addr vaddr, RiscvISA::PTE &pte); 96 void insertAt(RiscvISA::PTE &pte, unsigned Index, int _smallPages);
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/gem5/src/arch/sparc/ |
H A D | vtophys.cc | 89 PageTableEntry pte; local 118 pte.populate(betoh(entry), PageTableEntry::sun4v); 120 addr, pte.translate(addr)); 127 pte = tbe->pte; 129 pte.translate(addr)); 131 return pte.translate(addr);
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H A D | pagetable.cc | 48 entry4u = pte(); 66 pte.populate(entry4u);
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H A D | tlb.cc | 88 if (!t->pte.locked()) { 154 } while (tlb[x].pte.locked()); 179 new_entry->pte = PTE; 223 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 224 t->pte.size()); 250 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 315 if (tlb[x].valid && !tlb[x].pte.locked() && 351 return tlb[entry].pte(); 368 tag |= (uint64_t)~tlb[entry].pte 1061 PageTableEntry pte; local [all...] |
H A D | faults.cc | 633 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr); local 634 panic_if(!pte, "Tried to execute unmapped address %#x.\n", vaddr); 666 TlbEntry entry(p->pTable->pid(), alignedvaddr, pte->paddr, 667 pte->flags & EmulationPageTable::Uncacheable, 668 pte->flags & EmulationPageTable::ReadOnly); 676 insert(alignedvaddr, partition_id, context_id, false, entry.pte); 688 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr); local 689 if (!pte && p->fixupStackFault(vaddr)) 690 pte = p->pTable->lookup(vaddr); 691 panic_if(!pte, "Trie [all...] |
H A D | pagetable.hh | 252 pte = PageTableEntry(entry); 264 PageTableEntry pte; member in struct:SparcISA::TlbEntry 271 return pte.paddr();
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/gem5/src/arch/power/ |
H A D | tlb.cc | 91 PowerISA::PTE *pte = &table[index]; local 92 Addr Mask = pte->Mask; 94 Addr VPN = pte->VPN; 96 && (pte->G || (asn == pte->asid))) { 99 retval = pte; 128 PowerISA::PTE *pte = &table[index]; local 129 Addr Mask = pte->Mask; 131 Addr VPN = pte->VPN; 133 && (pte [all...] |
H A D | tlb.hh | 150 void insert(Addr vaddr, PowerISA::PTE &pte); 151 void insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages);
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/gem5/src/arch/alpha/ |
H A D | faults.cc | 199 const EmulationPageTable::Entry *pte = p->pTable->lookup(pc); local 200 panic_if(!pte, "Tried to execute unmapped address %#x.\n", pc); 203 TlbEntry entry(p->pTable->pid(), vaddr.page(), pte->paddr, 204 pte->flags & EmulationPageTable::Uncacheable, 205 pte->flags & EmulationPageTable::ReadOnly); 218 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr); local 219 if (!pte && p->fixupStackFault(vaddr)) 220 pte = p->pTable->lookup(vaddr); 221 panic_if(!pte, "Tried to access unmapped address %#x.\n", (Addr)vaddr); 222 TlbEntry entry(p->pTable->pid(), vaddr.page(), pte [all...] |
H A D | vtophys.cc | 106 PageTableEntry pte = local 108 if (pte.valid()) 109 paddr = pte.paddr() | vaddr.offset();
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H A D | remote_gdb.cc | 193 PageTableEntry pte = local 195 if (!pte.valid()) { 196 DPRINTF(GDBAcc, "acc: %#x pte is invalid\n", va);
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/gem5/src/mem/ |
H A D | page_table.cc | 178 for (auto &pte : pTable) { 181 paramOut(cp, "vaddr", pte.first); 182 paramOut(cp, "paddr", pte.second.paddr); 183 paramOut(cp, "flags", pte.second.flags);
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/gem5/src/gpu-compute/ |
H A D | gpu_tlb.cc | 799 const EmulationPageTable::Entry *pte = local 802 if (!pte && mode != BaseTLB::Execute) { 808 pte = p->pTable->lookup(vaddr); 811 if (!pte) { 819 alignedVaddr, pte->paddr); 822 pte->paddr, false, false); 1328 const EmulationPageTable::Entry *pte = p->pTable->lookup(vaddr); local 1329 if (!pte && sender_state->tlbMode != BaseTLB::Execute && 1331 pte = p->pTable->lookup(vaddr); 1334 if (pte) { 1531 const EmulationPageTable::Entry *pte = local [all...] |
/gem5/src/arch/arm/ |
H A D | tlb.hh | 232 void insert(Addr vaddr, TlbEntry &pte);
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