/gem5/src/arch/arm/ |
H A D | isa_device.cc | 61 DummyISADevice::setMiscReg(int misc_reg, RegVal val) argument 65 miscRegName[misc_reg]); 69 DummyISADevice::readMiscReg(int misc_reg) argument 71 warn("Returning zero for read from miscreg %s\n", miscRegName[misc_reg]);
|
H A D | isa_device.hh | 72 * @param misc_reg Register number (see miscregs.hh) 75 virtual void setMiscReg(int misc_reg, RegVal val) = 0; 80 * @param misc_reg Register number (see miscregs.hh) 83 virtual RegVal readMiscReg(int misc_reg) = 0; 103 void setMiscReg(int misc_reg, RegVal val) override; 104 RegVal readMiscReg(int misc_reg) override;
|
H A D | isa.cc | 428 ISA::readMiscRegNoEffect(int misc_reg) const 430 assert(misc_reg < NumMiscRegs); 432 const auto ® = lookUpMiscReg[misc_reg]; // bit masks 433 const auto &map = getMiscIndices(misc_reg); 441 miscRegName[misc_reg], val & reg.res0()); 445 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 452 ISA::readMiscReg(int misc_reg, ThreadContext *tc) 458 if (misc_reg == MISCREG_CPSR) { 459 cpsr = miscRegs[misc_reg]; 467 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTE [all...] |
H A D | pmu.cc | 194 PMU::setMiscReg(int misc_reg, RegVal val) argument 197 miscRegName[unflattenMiscReg(misc_reg)], val); 199 switch (unflattenMiscReg(misc_reg)) { 247 setCounterTypeRegister(misc_reg - MISCREG_PMEVTYPER0_EL0, val); 266 setCounterValue(misc_reg - MISCREG_PMEVCNTR0_EL0, val); 295 panic("Unexpected PMU register: %i\n", miscRegName[misc_reg]); 299 miscRegName[misc_reg]); 303 PMU::readMiscReg(int misc_reg) argument 305 RegVal val(readMiscRegInt(misc_reg)); 307 miscRegName[unflattenMiscReg(misc_reg)], va 312 readMiscRegInt(int misc_reg) argument [all...] |
/gem5/src/arch/riscv/ |
H A D | isa.cc | 76 ISA::hpmCounterEnabled(int misc_reg) const 78 int hpmcounter = misc_reg - MISCREG_CYCLE; 99 ISA::readMiscRegNoEffect(int misc_reg) const 101 if (misc_reg > NumMiscRegs || misc_reg < 0) { 103 panic("Illegal CSR index %#x\n", misc_reg); 106 DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg, 107 miscRegFile[misc_reg]); 108 return miscRegFile[misc_reg]; 112 ISA::readMiscReg(int misc_reg, ThreadContex argument 169 setMiscRegNoEffect(int misc_reg, RegVal val) argument 180 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) argument [all...] |
H A D | isa.hh | 77 RegVal readMiscRegNoEffect(int misc_reg) const; 78 RegVal readMiscReg(int misc_reg, ThreadContext *tc); 79 void setMiscRegNoEffect(int misc_reg, RegVal val); 80 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
|
/gem5/src/arch/alpha/ |
H A D | isa.cc | 78 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const argument 80 switch (misc_reg) { 92 assert(misc_reg < NumInternalProcRegs); 93 return ipr[misc_reg]; 98 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 100 switch (misc_reg) { 112 return readIpr(misc_reg, tc); 117 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) 119 switch (misc_reg) { 136 assert(misc_reg < NumInternalProcReg [all...] |
H A D | isa.hh | 77 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 78 RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 80 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0); 81 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc,
|
/gem5/src/arch/power/ |
H A D | isa.hh | 65 readMiscRegNoEffect(int misc_reg) const 72 readMiscReg(int misc_reg, ThreadContext *tc) argument 79 setMiscRegNoEffect(int misc_reg, RegVal val) argument 85 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) argument
|
/gem5/src/arch/mips/ |
H A D | isa.hh | 90 void updateCP0ReadView(int misc_reg, ThreadID tid) { } argument 91 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const; 94 RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0); 96 RegVal filterCP0Write(int misc_reg, int reg_sel, RegVal val); 97 void setRegMask(int misc_reg, RegVal val, ThreadID tid = 0); 98 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0); 101 void setMiscReg(int misc_reg, RegVal val,
|
H A D | isa.cc | 421 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const argument 423 unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 426 misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], 427 miscRegFile[misc_reg][reg_sel]); 428 return miscRegFile[misc_reg][reg_sel]; 435 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) argument 437 unsigned reg_sel = (bankType[misc_reg] == perThreadContext) 441 misc_reg / 448 setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument 461 setRegMask(int misc_reg, RegVal val, ThreadID tid) argument 476 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) argument 499 filterCP0Write(int misc_reg, int reg_sel, RegVal val) argument [all...] |
/gem5/src/arch/arm/insts/ |
H A D | misc64.cc | 87 MiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg, argument 93 if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) { 101 checkEL2Trap(tc, misc_reg, el, &is_vfp_neon)) { 110 checkEL3Trap(tc, misc_reg, el, &is_vfp_neon)) { 122 MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument 128 switch (misc_reg) { 143 MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument 155 switch (misc_reg) { 292 MiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg, argument 300 switch (misc_reg) { [all...] |
H A D | misc64.hh | 132 Fault trap(ThreadContext *tc, MiscRegIndex misc_reg, 135 bool checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 138 bool checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 141 bool checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 216 MiscRegIndex misc_reg, bool misc_read, 220 fullMnemonic(full_mnem), miscReg(misc_reg), imm(_imm), 215 MiscRegImplDefined64(const char *mnem, ExtMachInst _machInst, MiscRegIndex misc_reg, bool misc_read, uint32_t _imm, const std::string full_mnem, bool _warning) argument
|
/gem5/src/cpu/checker/ |
H A D | thread_context.hh | 425 readMiscRegNoEffect(RegIndex misc_reg) const override 427 return actualTC->readMiscRegNoEffect(misc_reg); 431 readMiscReg(RegIndex misc_reg) override 433 return actualTC->readMiscReg(misc_reg); 437 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 440 " and O3..\n", misc_reg); 441 checkerTC->setMiscRegNoEffect(misc_reg, val); 442 actualTC->setMiscRegNoEffect(misc_reg, val); 446 setMiscReg(RegIndex misc_reg, RegVal val) override 449 " and O3..\n", misc_reg); [all...] |
H A D | cpu.hh | 455 readMiscRegNoEffect(int misc_reg) const 457 return thread->readMiscRegNoEffect(misc_reg); 461 readMiscReg(int misc_reg) override 463 return thread->readMiscReg(misc_reg); 467 setMiscRegNoEffect(int misc_reg, RegVal val) argument 470 misc_reg); 471 miscRegIdxs.push(misc_reg); 472 return thread->setMiscRegNoEffect(misc_reg, val); 476 setMiscReg(int misc_reg, RegVal val) override 479 misc_reg); [all...] |
/gem5/src/cpu/minor/ |
H A D | dyn_inst.cc | 146 RegIndex misc_reg = reg.index(); local 150 os << 'm' << misc_reg << '(' << TheISA::miscRegName[misc_reg] << 153 os << 'n' << misc_reg; local
|
H A D | exec_context.hh | 356 readMiscRegNoEffect(int misc_reg) const 358 return thread.readMiscRegNoEffect(misc_reg); 362 readMiscReg(int misc_reg) override 364 return thread.readMiscReg(misc_reg); 368 setMiscReg(int misc_reg, RegVal val) override 370 thread.setMiscReg(misc_reg, val);
|
/gem5/src/cpu/o3/ |
H A D | thread_context.hh | 385 readMiscRegNoEffect(RegIndex misc_reg) const override 387 return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); 393 readMiscReg(RegIndex misc_reg) override 395 return cpu->readMiscReg(misc_reg, thread->threadId()); 399 void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override; 403 void setMiscReg(RegIndex misc_reg, RegVal val) override;
|
H A D | thread_context_impl.hh | 346 O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val) argument 348 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId()); 355 O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val) argument 357 cpu->setMiscReg(misc_reg, val, thread->threadId());
|
H A D | dyn_inst.hh | 140 readMiscReg(int misc_reg) override 142 return this->cpu->readMiscReg(misc_reg, this->threadNumber); 149 setMiscReg(int misc_reg, RegVal val) override 158 if (_destMiscRegIdx[idx] == misc_reg) { 165 _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
|
/gem5/src/dev/arm/ |
H A D | generic_timer.hh | 226 void setMiscReg(int misc_reg, unsigned cpu, RegVal val); 227 RegVal readMiscReg(int misc_reg, unsigned cpu); 289 void setMiscReg(int misc_reg, RegVal val) override; 290 RegVal readMiscReg(int misc_reg) override;
|
H A D | gic_v3_cpu_interface.hh | 341 RegVal readBankedMiscReg(MiscRegIndex misc_reg) const; 342 void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const; 350 RegVal readMiscReg(int misc_reg) override; 351 void setMiscReg(int misc_reg, RegVal val) override;
|
/gem5/src/cpu/ |
H A D | thread_context.hh | 286 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0; 288 virtual RegVal readMiscReg(RegIndex misc_reg) = 0; 290 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0; 292 virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
|
H A D | simple_thread.hh | 541 readMiscRegNoEffect(RegIndex misc_reg) const override 543 return isa->readMiscRegNoEffect(misc_reg); 547 readMiscReg(RegIndex misc_reg) override 549 return isa->readMiscReg(misc_reg, this); 553 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override 555 return isa->setMiscRegNoEffect(misc_reg, val); 559 setMiscReg(RegIndex misc_reg, RegVal val) override 561 return isa->setMiscReg(misc_reg, val, this);
|
H A D | exec_context.hh | 208 virtual RegVal readMiscReg(int misc_reg) = 0; 214 virtual void setMiscReg(int misc_reg, RegVal val) = 0;
|