arch/arm/isa.cc

428 ISA::readMiscRegNoEffect(int misc_reg) const
430     assert(misc_reg < NumMiscRegs);
432     const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
433     const auto &map = getMiscIndices(misc_reg);
441                 miscRegName[misc_reg], val & reg.res0());
445                 miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
452 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
458     if (misc_reg == MISCREG_CPSR) {
459         cpsr = miscRegs[misc_reg];
467     if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
468         if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
470                  miscRegName[misc_reg]);
473                   miscRegName[misc_reg]);
477     switch (unflattenMiscReg(misc_reg)) {
509                     miscRegName[misc_reg], val);
518         return readMiscRegNoEffect(misc_reg) | 0x80000000;
525             return readMiscRegNoEffect(misc_reg);
583         return pmu->readMiscReg(misc_reg);
688             RegVal val = readMiscRegNoEffect(misc_reg);
738         return getGenericTimer(tc).readMiscReg(misc_reg);
743         return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
749     return readMiscRegNoEffect(misc_reg);
753 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
755     assert(misc_reg < NumMiscRegs);
757     const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
758     const auto &map = getMiscIndices(misc_reg);
766                 misc_reg, lower, upper, v);
770                 misc_reg, lower, v);
775 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
782     if (misc_reg == MISCREG_CPSR) {
799                 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
817         if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
818             if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
820                     miscRegName[misc_reg], val);
823                     miscRegName[misc_reg], val);
826         switch (unflattenMiscReg(misc_reg)) {
854                         miscRegName[misc_reg], newVal);
868                         miscRegName[misc_reg], newVal);
891                         miscRegName[misc_reg], newVal);
906                         miscRegName[misc_reg], newVal);
969                 misc_reg = MISCREG_FPSCR;
986                 misc_reg = MISCREG_FPSCR;
993                 misc_reg = MISCREG_CPSR;
1000                 misc_reg = MISCREG_FPSCR;
1007                 misc_reg = MISCREG_FPSCR;
1619             pmu->setMiscReg(misc_reg, newVal);
1646             misc_reg = MISCREG_DFAR_S;
1649             misc_reg = MISCREG_IFAR_S;
1666               switch(misc_reg) {
1733                    miscRegName[misc_reg]);
1876                 misc_reg = MISCREG_CPSR;
1893                 misc_reg = MISCREG_CPSR;
1901                 misc_reg = MISCREG_CPSR;
1912                 misc_reg = MISCREG_CPSR;
1933                 switch(misc_reg) {
2002                      miscRegName[misc_reg]);
2064                  miscRegName[misc_reg], uint32_t(val));
2075             getGenericTimer(tc).setMiscReg(misc_reg, newVal);
2080             getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
2090     setMiscRegNoEffect(misc_reg, newVal);