Searched refs:inst (Results 1 - 25 of 148) sorted by relevance

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/gem5/util/
H A Ddecode_inst_trace.py43 # generated the Python package for the inst messages. This can
45 # protoc --python_out=. inst.proto
55 print "Did not find protobuf inst definitions, attempting to generate"
58 'src/proto/inst.proto'])
60 print "Generated inst proto definitions"
70 print "Failed to import inst proto definitions"
112 inst = inst_pb2.Inst()
114 # Decode the inst messages until we hit the end of the file
116 while protolib.decodeMessage(proto_in, inst):
118 if inst
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/gem5/src/cpu/minor/
H A Dexecute.cc216 Execute::tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch) argument
218 ThreadContext *thread = cpu.getContext(inst->id.threadId);
219 const TheISA::PCState &pc_before = inst->pc;
225 !inst->isFault() &&
226 inst->isLastOpInInst() &&
227 (inst->staticInst->isSerializeAfter() ||
228 inst->staticInst->isSquashAfter() ||
229 inst->staticInst->isIprAccess());
244 TheISA::advancePC(target, inst->staticInst);
251 if (inst
295 updateBranchData( ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const TheISA::PCState &target, BranchData &branch) argument
321 handleMemResponse(MinorDynInstPtr inst, LSQ::LSQRequestPtr response, BranchData &branch, Fault &fault) argument
448 executeMemRefInst(MinorDynInstPtr inst, BranchData &branch, bool &passed_predicate, Fault &fault) argument
572 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex]; local
857 doInstCommitAccounting(MinorDynInstPtr inst) argument
890 commitInst(MinorDynInstPtr inst, bool early_memory_issue, BranchData &branch, Fault &fault, bool &committed, bool &completed_mem_issue) argument
1093 MinorDynInstPtr inst = head_inflight_inst->inst; local
1505 MinorDynInstPtr inst = getInput(tid)->insts[input_index]; local
1700 MinorDynInstPtr inst = head_inflight_inst->inst; local
1864 instIsRightStream(MinorDynInstPtr inst) argument
1870 instIsHeadInst(MinorDynInstPtr inst) argument
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H A Dfetch2.cc128 MinorDynInstPtr inst = branch.inst; local
131 if (inst->isFault() || !inst->triedToPredict)
153 DPRINTF(Branch, "Unpredicted branch seen inst: %s\n", *inst);
154 branchPredictor.squash(inst->id.fetchSeqNum,
155 branch.target, true, inst->id.threadId);
158 branchPredictor.update(inst->id.fetchSeqNum,
159 inst
188 predictBranch(MinorDynInstPtr inst, BranchData &branch) argument
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H A Dscoreboard.cc110 Scoreboard::markupInstDests(MinorDynInstPtr inst, Cycles retire_time, argument
113 if (inst->isFault())
116 StaticInstPtr staticInst = inst->staticInst;
131 inst->flatDestRegIdx[dest_index] = reg;
137 if (inst->id.execSeqNum > writingInst[index]) {
138 writingInst[index] = inst->id.execSeqNum;
139 fuIndices[index] = inst->fuIndex;
142 DPRINTF(MinorScoreboard, "Marking up inst: %s"
144 *inst, index, numResults[index], returnCycle[index]);
147 inst
154 execSeqNumToWaitFor(MinorDynInstPtr inst, ThreadContext *thread_context) argument
183 clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable) argument
218 canInstIssue(MinorDynInstPtr inst, const std::vector<Cycles> *src_reg_relative_latencies, const std::vector<bool> *cant_forward_from_fu_indices, Cycles now, ThreadContext *thread_context) argument
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/gem5/src/cpu/o3/
H A Dmem_dep_unit_impl.hh174 MemDepUnit<MemDepPred, Impl>::insert(const DynInstPtr &inst) argument
176 ThreadID tid = inst->threadNumber;
178 MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
182 std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
187 instList[tid].push_back(inst);
194 if ((inst->isLoad() || inst->isAtomic()) && loadBarrier) {
198 } else if ((inst->isStore() || inst->isAtomic()) && storeBarrier) {
203 producing_store = depPred.checkInst(inst
271 insertNonSpec(const DynInstPtr &inst) argument
343 regsReady(const DynInstPtr &inst) argument
366 nonSpecInstReady(const DynInstPtr &inst) argument
379 reschedule(const DynInstPtr &inst) argument
407 completed(const DynInstPtr &inst) argument
431 completeBarrier(const DynInstPtr &inst) argument
452 wakeDependents(const DynInstPtr &inst) argument
552 issue(const DynInstPtr &inst) argument
562 findInHash(const DynInstConstPtr &inst) argument
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H A Diew_impl.hh499 DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid) argument
503 "\n", tid, inst->seqNum, inst->pcState() );
506 inst->seqNum < toCommit->squashedSeqNum[tid]) {
508 toCommit->squashedSeqNum[tid] = inst->seqNum;
509 toCommit->branchTaken[tid] = inst->pcState().branching();
511 TheISA::PCState pc = inst->pcState();
512 TheISA::advancePC(pc, inst->staticInst);
515 toCommit->mispredictInst[tid] = inst;
525 DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadI argument
588 wakeDependents(const DynInstPtr& inst) argument
595 rescheduleMemInst(const DynInstPtr& inst) argument
602 replayMemInst(const DynInstPtr& inst) argument
609 blockMemInst(const DynInstPtr& inst) argument
623 instToCommit(const DynInstPtr& inst) argument
668 DynInstPtr inst = NULL; local
971 DynInstPtr inst; local
1186 int inst = 0; local
1232 DynInstPtr inst = instQueue.getInstToExecute(); local
1463 DynInstPtr inst = toCommit->insts[inst_num]; local
1634 updateExeInstStats(const DynInstPtr& inst) argument
1666 checkMisprediction(const DynInstPtr& inst) argument
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H A Dmem_dep_unit.hh121 void insert(const DynInstPtr &inst);
124 void insertNonSpec(const DynInstPtr &inst);
130 void regsReady(const DynInstPtr &inst);
133 void nonSpecInstReady(const DynInstPtr &inst);
136 void reschedule(const DynInstPtr &inst);
144 void completed(const DynInstPtr &inst);
147 void completeBarrier(const DynInstPtr &inst);
150 void wakeDependents(const DynInstPtr &inst);
162 void issue(const DynInstPtr &inst);
182 : inst(new_ins
211 DynInstPtr inst; member in class:MemDepUnit::MemDepEntry
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H A Ddep_graph.hh54 : inst(NULL), next(NULL)
57 DynInstPtr inst; member in class:DependencyEntry
96 { dependGraph[idx].inst = new_inst; }
100 { dependGraph[idx].inst = NULL; }
169 prev->inst = NULL;
174 if (dependGraph[i].inst) {
175 dependGraph[i].inst = NULL;
194 new_entry->inst = new_inst;
222 while (curr->inst != inst_to_remove) {
236 curr->inst
247 DynInstPtr inst = NULL; local
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H A Dlsq_unit_impl.hh67 inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
79 lsqPtr->writeback(inst, pkt);
81 assert(inst->savedReq);
82 inst->savedReq->writebackDone();
116 DynInstPtr inst = state->inst; local
118 cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
125 if (!inst->isSquashed()) {
129 assert(inst->isLoad() || inst
276 insert(const DynInstPtr &inst) argument
451 checkViolations(typename LoadQueue::iterator& loadIt, const DynInstPtr& inst) argument
532 executeLoad(const DynInstPtr &inst) argument
756 DynInstPtr inst = storeWBIt->instruction(); local
949 writeback(const DynInstPtr &inst, PacketPtr pkt) argument
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/gem5/src/sim/
H A Dfaults.cc43 void FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst) argument
52 void UnimpFault::invoke(ThreadContext * tc, const StaticInstPtr &inst) argument
57 void ReExec::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument
62 void SyscallRetryFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument
67 void GenericPageTableFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument
79 void GenericAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument
H A Dfaults.hh48 virtual void invoke(ThreadContext * tc, const StaticInstPtr &inst =
64 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
73 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
89 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
100 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
112 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
/gem5/src/arch/hsail/
H A Dgpu_decoder.hh59 decode(RawMachInst inst) argument
61 return inst < decodedInsts.size() ? decodedInsts.at(inst) : nullptr;
/gem5/ext/pybind11/tests/
H A Dconstructor_stats.h84 void copy_created(void *inst) { argument
85 created(inst);
89 void move_created(void *inst) { argument
90 created(inst);
94 void default_created(void *inst) { argument
95 created(inst);
99 void created(void *inst) { argument
100 ++_instances[inst];
103 void destroyed(void *inst) { argument
104 if (--_instances[inst] <
201 track_copy_created(T *inst) argument
202 track_move_created(T *inst) argument
213 track_default_created(T *inst, Values &&...values) argument
218 track_created(T *inst, Values &&...values) argument
223 track_destroyed(T *inst) argument
238 print_constr_details(T *inst, const std::string &action, Output &&...output) argument
244 print_copy_created(T *inst, Values &&...values) argument
248 print_move_created(T *inst, Values &&...values) argument
252 print_copy_assigned(T *inst, Values &&...values) argument
256 print_move_assigned(T *inst, Values &&...values) argument
260 print_default_created(T *inst, Values &&...values) argument
264 print_created(T *inst, Values &&...values) argument
268 print_destroyed(T *inst, Values &&...values) argument
272 print_values(T *inst, Values &&...values) argument
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/gem5/src/arch/alpha/
H A Dstacktrace.hh72 bool decodeSave(MachInst inst, int &reg, int &disp);
73 bool decodeStack(MachInst inst, int &disp);
79 StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
90 bool trace(ThreadContext *tc, const StaticInstPtr &inst);
114 StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst) argument
116 if (!inst->isCall() && !inst->isReturn())
122 trace(tc, !inst->isReturn());
/gem5/src/arch/arm/
H A Dstacktrace.hh74 bool decodeSave(MachInst inst, int &reg, int &disp);
75 bool decodeStack(MachInst inst, int &disp);
81 StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
91 bool trace(ThreadContext *tc, const StaticInstPtr &inst);
109 StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst) argument
111 if (!inst->isCall() && !inst->isReturn())
117 trace(tc, !inst->isReturn());
/gem5/src/arch/mips/
H A Dstacktrace.hh71 bool decodeSave(MachInst inst, int &reg, int &disp);
72 bool decodeStack(MachInst inst, int &disp);
78 StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
88 bool trace(ThreadContext *tc, const StaticInstPtr &inst);
110 StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst) argument
112 if (!inst->isCall() && !inst->isReturn())
118 trace(tc, !inst->isReturn());
H A Dstacktrace.cc99 StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst) argument
102 trace(_tc, inst);
128 StackTrace::decodeStack(MachInst inst, int &disp) argument
156 if ((inst & mem_mask) == lda_pattern)
157 disp = -sext<16>(inst & lda_disp_mask);
158 else if ((inst & intop_mask) == addq_pattern)
159 disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
160 else if ((inst & intop_mask) == subq_pattern)
161 disp = int((inst & intop_disp_mask) >> intop_disp_shift);
169 StackTrace::decodeSave(MachInst inst, in argument
205 MachInst inst = tc->getVirtProxy().read<MachInst>(pc); local
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/gem5/src/arch/x86/
H A Dstacktrace.hh71 bool decodeSave(MachInst inst, int &reg, int &disp);
72 bool decodeStack(MachInst inst, int &disp);
78 StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
88 bool trace(ThreadContext *tc, const StaticInstPtr &inst);
110 StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst) argument
112 if (!inst->isCall() && !inst->isReturn())
118 trace(tc, !inst->isReturn());
/gem5/tests/test-progs/insttest/src/riscv/
H A Dinsttest.h39 #define IOP(inst, rd, rs1, imm) \
40 asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "i" (imm))
42 #define ROP(inst, rd, rs1, rs2) \
43 asm volatile(inst " %0,%1,%2" : "=r" (rd) : "r" (rs1), "r" (rs2))
45 #define FROP(inst, fd, fs1, fs2) \
46 asm volatile(inst " %0,%1,%2" : "=f" (fd) : "f" (fs1), "f" (fs2))
48 #define FR4OP(inst, fd, fs1, fs2, fs3) \
49 asm volatile(inst " %0,%1,%2,%3" \
/gem5/src/arch/riscv/
H A Dstacktrace.hh67 bool decodeSave(MachInst inst, int &reg, int &disp);
68 bool decodeStack(MachInst inst, int &disp);
74 StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
90 bool trace(ThreadContext *tc, const StaticInstPtr &inst);
124 StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst) argument
126 if (!inst->isCall() && !inst->isReturn())
132 trace(tc, !inst->isReturn());
H A Dfaults.hh111 virtual void invokeSE(ThreadContext *tc, const StaticInstPtr &inst);
112 void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
124 void invoke(ThreadContext *tc, const StaticInstPtr &inst =
141 InstFault(FaultName n, const ExtMachInst inst) argument
142 : RiscvFault(n, false, INST_ILLEGAL), _inst(inst)
151 UnknownInstFault(const ExtMachInst inst) argument
152 : InstFault("Unknown instruction", inst)
155 void invokeSE(ThreadContext *tc, const StaticInstPtr &inst) override;
164 IllegalInstFault(std::string r, const ExtMachInst inst) argument
165 : InstFault("Illegal instruction", inst)
177 UnimplementedFault(std::string name, const ExtMachInst inst) argument
191 IllegalFrmFault(uint8_t r, const ExtMachInst inst) argument
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H A Dfaults.cc48 RiscvFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) argument
54 RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument
135 invokeSE(tc, inst);
136 advancePC(pcState, inst);
141 void Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument
156 UnknownInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) argument
158 panic("Unknown instruction 0x%08x at pc 0x%016llx", inst->machInst,
163 IllegalInstFault::invokeSE(ThreadContext *tc, const StaticInstPtr &inst) argument
165 panic("Illegal instruction 0x%08x at pc 0x%016llx: %s", inst->machInst,
171 const StaticInstPtr &inst)
170 invokeSE(ThreadContext *tc, const StaticInstPtr &inst) argument
178 invokeSE(ThreadContext *tc, const StaticInstPtr &inst) argument
185 invokeSE(ThreadContext *tc, const StaticInstPtr &inst) argument
191 invokeSE(ThreadContext *tc, const StaticInstPtr &inst) argument
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/gem5/src/arch/power/
H A Dstacktrace.hh67 bool decodeSave(MachInst inst, int &reg, int &disp);
68 bool decodeStack(MachInst inst, int &disp);
74 StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
90 bool trace(ThreadContext *tc, const StaticInstPtr &inst);
124 StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst) argument
126 if (!inst->isCall() && !inst->isReturn())
132 trace(tc, !inst->isReturn());
/gem5/tests/test-progs/asmtest/src/riscv/isa/macros/scalar/
H A Dtest_macros.h46 #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \
49 inst x30, x1, SEXT_IMM(imm); \
52 #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \
55 inst x1, x1, SEXT_IMM(imm); \
58 #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
62 inst x30, x1, SEXT_IMM(imm); \
70 #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \
75 inst x30, x1, SEXT_IMM(imm); \
81 #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \
83 inst x
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/gem5/src/arch/sparc/
H A Ddecoder.hh66 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) argument
68 emi = inst;
73 if (inst & (1 << 13)) {
77 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))

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