cpu/o3/mem_dep_unit_impl.hh

174 MemDepUnit<MemDepPred, Impl>::insert(const DynInstPtr &inst)
176     ThreadID tid = inst->threadNumber;
178     MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
182         std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
187     instList[tid].push_back(inst);
194     if ((inst->isLoad() || inst->isAtomic()) && loadBarrier) {
198     } else if ((inst->isStore() || inst->isAtomic()) && storeBarrier) {
203         producing_store = depPred.checkInst(inst->instAddr());
222         DPRINTF(MemDepUnit, "No dependency for inst PC "
223                 "%s [sn:%lli].\n", inst->pcState(), inst->seqNum);
227         if (inst->readyToIssue()) {
235                 "inst PC %s is dependent on [sn:%lli].\n",
236                 inst->pcState(), producing_store);
238         if (inst->readyToIssue()) {
243         inst->clearCanIssue();
248         if (inst->isLoad()) {
255     if (inst->isStore() || inst->isAtomic()) {
257                 inst->pcState(), inst->seqNum);
259         depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
262     } else if (inst->isLoad()) {
271 MemDepUnit<MemDepPred, Impl>::insertNonSpec(const DynInstPtr &inst)
273     ThreadID tid = inst->threadNumber;
275     MemDepEntryPtr inst_entry = std::make_shared<MemDepEntry>(inst);
279         std::pair<InstSeqNum, MemDepEntryPtr>(inst->seqNum, inst_entry));
285     instList[tid].push_back(inst);
291     if (inst->isStore() || inst->isAtomic()) {
293                 inst->pcState(), inst->seqNum);
295         depPred.insertStore(inst->instAddr(), inst->seqNum, inst->threadNumber);
298     } else if (inst->isLoad()) {
343 MemDepUnit<MemDepPred, Impl>::regsReady(const DynInstPtr &inst)
347             inst->pcState(), inst->seqNum);
349     MemDepEntryPtr inst_entry = findInHash(inst);
366 MemDepUnit<MemDepPred, Impl>::nonSpecInstReady(const DynInstPtr &inst)
370             inst->pcState(), inst->seqNum);
372     MemDepEntryPtr inst_entry = findInHash(inst);
379 MemDepUnit<MemDepPred, Impl>::reschedule(const DynInstPtr &inst)
381     instsToReplay.push_back(inst);
407 MemDepUnit<MemDepPred, Impl>::completed(const DynInstPtr &inst)
410             inst->pcState(), inst->seqNum);
412     ThreadID tid = inst->threadNumber;
415     MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
431 MemDepUnit<MemDepPred, Impl>::completeBarrier(const DynInstPtr &inst)
433     wakeDependents(inst);
434     completed(inst);
436     InstSeqNum barr_sn = inst->seqNum;
437     DPRINTF(MemDepUnit, "barrier completed: %s SN:%lli\n", inst->pcState(),
438             inst->seqNum);
439     if (inst->isMemBarrier()) {
444     } else if (inst->isWriteBarrier()) {
452 MemDepUnit<MemDepPred, Impl>::wakeDependents(const DynInstPtr &inst)
455     if (!inst->isStore() && !inst->isAtomic() && !inst->isMemBarrier() &&
456         !inst->isWriteBarrier()) {
460     MemDepEntryPtr inst_entry = findInHash(inst);
465         if (!woken_inst->inst) {
470         DPRINTF(MemDepUnit, "Waking up a dependent inst, "
472                 woken_inst->inst->seqNum);
509         DPRINTF(MemDepUnit, "Squashing inst [sn:%lli]\n",
552 MemDepUnit<MemDepPred, Impl>::issue(const DynInstPtr &inst)
555             inst->instAddr(), inst->seqNum);
557     depPred.issued(inst->instAddr(), inst->seqNum, inst->isStore());
562 MemDepUnit<MemDepPred, Impl>::findInHash(const DynInstConstPtr &inst)
564     MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
576             "to the ready list.\n", woken_inst_entry->inst->seqNum);
580     iqPtr->addReadyMemInst(woken_inst_entry->inst);