cpu/o3/lsq_unit_impl.hh

67       inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
79     lsqPtr->writeback(inst, pkt);
81     assert(inst->savedReq);
82     inst->savedReq->writebackDone();
116     DynInstPtr inst = state->inst;
118     cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
125     if (!inst->isSquashed()) {
129             assert(inst->isLoad() || inst->isStoreConditional() ||
130                    inst->isAtomic());
131             writeback(inst, state->request()->mainPacket());
132             if (inst->isStore() || inst->isAtomic()) {
137         } else if (inst->isStore()) {
276 LSQUnit<Impl>::insert(const DynInstPtr &inst)
278     assert(inst->isMemRef());
280     assert(inst->isLoad() || inst->isStore() || inst->isAtomic());
282     if (inst->isLoad()) {
283         insertLoad(inst);
285         insertStore(inst);
288     inst->setInLSQ();
412         DPRINTF(LSQUnit, "-- inst [sn:%lli] to pktAddr:%#x\n",
452         const DynInstPtr& inst)
454     Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
455     Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
474             if (inst->isLoad()) {
481                         DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] "
483                                 inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
489                             "Detected fault with inst [sn:%lli] and "
491                             inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
500                         inst_eff_addr1, inst->seqNum, ld_inst->seqNum);
508                 DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and "
510                         inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
517                     "inst [sn:%lli] and [sn:%lli] at address %#x\n",
518                     inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
532 LSQUnit<Impl>::executeLoad(const DynInstPtr &inst)
539             inst->pcState(), inst->seqNum);
541     assert(!inst->isSquashed());
543     load_fault = inst->initiateAcc();
545     if (load_fault == NoFault && !inst->readMemAccPredicate()) {
546         assert(inst->readPredicate());
547         inst->setExecuted();
548         inst->completeAcc(nullptr);
549         iewStage->instToCommit(inst);
554     if (inst->isTranslationDelayed() && load_fault == NoFault)
557     if (load_fault != NoFault && inst->translationCompleted() &&
558         inst->savedReq->isPartialFault() && !inst->savedReq->isComplete()) {
559         assert(inst->savedReq->isSplit());
569     if (load_fault != NoFault || !inst->readPredicate()) {
574         if (!inst->readPredicate())
575             inst->forwardOldRegs();
577                 inst->seqNum,
579         if (!(inst->hasRequest() && inst->strictlyOrdered()) ||
580             inst->isAtCommit()) {
581             inst->setExecuted();
583         iewStage->instToCommit(inst);
586         if (inst->effAddrValid()) {
587             auto it = inst->lqIt;
591                 return checkViolations(it, inst);
756         DynInstPtr inst = storeWBIt->instruction();
760         assert(!inst->memData);
761         inst->memData = new uint8_t[req->_size];
764             memset(inst->memData, 0, req->_size);
766             memcpy(inst->memData, storeWBIt->data(), req->_size);
773             state->inst = inst;
776             if (inst->isStoreConditional() || inst->isAtomic()) {
785                 storeWBIt.idx(), inst->pcState(),
786                 req->request()->getPaddr(), (int)*(inst->memData),
787                 inst->seqNum);
790         if (inst->isStoreConditional()) {
794             inst->recordResult(false);
795             bool success = TheISA::handleLockedWrite(inst.get(),
797             inst->recordResult(true);
805                         inst->seqNum);
807                 WritebackEvent *wb = new WritebackEvent(inst,
820             assert(!inst->isStoreConditional());
824             main_pkt->dataStatic(inst->memData);
840                     inst->seqNum);
949 LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt)
954     if (inst->isSquashed()) {
955         assert(!inst->isStore());
960     if (!inst->isExecuted()) {
961         inst->setExecuted();
963         if (inst->fault == NoFault) {
965             inst->completeAcc(pkt);
973             assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr ||
974                    inst->savedReq->isPartialFault());
977                     "due to pending fault.\n", inst->seqNum);
982     iewStage->instToCommit(inst);
987     iewStage->checkMisprediction(inst);
1114         const DynInstPtr &inst(e.instruction());
1115         cprintf("%s.[sn:%llu] ", inst->pcState(), inst->seqNum);
1123         const DynInstPtr &inst(e.instruction());
1124         cprintf("%s.[sn:%llu] ", inst->pcState(), inst->seqNum);