cpu/o3/iew_impl.hh

499 DefaultIEW<Impl>::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
503             "\n", tid, inst->seqNum, inst->pcState() );
506             inst->seqNum < toCommit->squashedSeqNum[tid]) {
508         toCommit->squashedSeqNum[tid] = inst->seqNum;
509         toCommit->branchTaken[tid] = inst->pcState().branching();
511         TheISA::PCState pc = inst->pcState();
512         TheISA::advancePC(pc, inst->staticInst);
515         toCommit->mispredictInst[tid] = inst;
525 DefaultIEW<Impl>::squashDueToMemOrder(const DynInstPtr& inst, ThreadID tid)
528             "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum);
529     // Need to include inst->seqNum in the following comparison to cover the
536             inst->seqNum <= toCommit->squashedSeqNum[tid]) {
539         toCommit->squashedSeqNum[tid] = inst->seqNum;
540         toCommit->pc[tid] = inst->pcState();
588 DefaultIEW<Impl>::wakeDependents(const DynInstPtr& inst)
590     instQueue.wakeDependents(inst);
595 DefaultIEW<Impl>::rescheduleMemInst(const DynInstPtr& inst)
597     instQueue.rescheduleMemInst(inst);
602 DefaultIEW<Impl>::replayMemInst(const DynInstPtr& inst)
604     instQueue.replayMemInst(inst);
609 DefaultIEW<Impl>::blockMemInst(const DynInstPtr& inst)
611     instQueue.blockMemInst(inst);
623 DefaultIEW<Impl>::instToCommit(const DynInstPtr& inst)
646     (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
668     DynInstPtr inst = NULL;
671         inst = insts[tid].front();
676                 "dispatch skidBuffer %i\n",tid, inst->seqNum,
677                 inst->pcState(),tid);
679         skidBuffer[tid].push(inst);
971     DynInstPtr inst;
981         inst = insts_to_dispatch.front();
989         assert(inst);
993                 tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1000         if (inst->isSquashed()) {
1009             if (inst->isLoad()) {
1012             if (inst->isStore() || inst->isAtomic()) {
1037         // Check LSQ if inst is LD/ST
1038         if ((inst->isAtomic() && ldstQueue.sqFull(tid)) ||
1039             (inst->isLoad() && ldstQueue.lqFull(tid)) ||
1040             (inst->isStore() && ldstQueue.sqFull(tid))) {
1042                     inst->isLoad() ? "LQ" : "SQ");
1057         if (inst->isAtomic()) {
1061             ldstQueue.insertStore(inst);
1068             inst->setCanCommit();
1069             instQueue.insertNonSpec(inst);
1075         } else if (inst->isLoad()) {
1081             ldstQueue.insertLoad(inst);
1088         } else if (inst->isStore()) {
1092             ldstQueue.insertStore(inst);
1096             if (inst->isStoreConditional()) {
1101                 inst->setCanCommit();
1102                 instQueue.insertNonSpec(inst);
1111         } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1113             inst->setCanCommit();
1114             instQueue.insertBarrier(inst);
1116         } else if (inst->isNop()) {
1120             inst->setIssued();
1121             inst->setExecuted();
1122             inst->setCanCommit();
1124             instQueue.recordProducer(inst);
1130             assert(!inst->isExecuted());
1134         if (add_to_iq && inst->isNonSpeculative()) {
1139             inst->setCanCommit();
1142             instQueue.insertNonSpec(inst);
1152             instQueue.insert(inst);
1162         inst->dispatchTick = curTick() - inst->fetchTick;
1164         ppDispatch->notify(inst);
1186     int inst = 0;
1190     while (fromIssue->insts[inst]) {
1192         if (inst%3==0) std::cout << "\n\t";
1194         std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1195              << " TN: " << fromIssue->insts[inst]->threadNumber
1196              << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1198         inst++;
1232         DynInstPtr inst = instQueue.getInstToExecute();
1235                 inst->pcState(), inst->threadNumber,inst->seqNum);
1239         ppExecute->notify(inst);
1242         if (inst->isSquashed()) {
1244                          " [sn:%llu]\n", inst->pcState(), inst->threadNumber,
1245                          inst->seqNum);
1249             inst->setExecuted();
1253             inst->setCanCommit();
1265         if (inst->isMemRef()) {
1270             if (inst->isAtomic()) {
1272                 fault = ldstQueue.executeStore(inst);
1274                 if (inst->isTranslationDelayed() &&
1280                     instQueue.deferMemInst(inst);
1283             } else if (inst->isLoad()) {
1286                 fault = ldstQueue.executeLoad(inst);
1288                 if (inst->isTranslationDelayed() &&
1294                     instQueue.deferMemInst(inst);
1298                 if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1299                     inst->fault = NoFault;
1301             } else if (inst->isStore()) {
1302                 fault = ldstQueue.executeStore(inst);
1304                 if (inst->isTranslationDelayed() &&
1310                     instQueue.deferMemInst(inst);
1315                 if (fault != NoFault || !inst->readPredicate() ||
1316                         !inst->isStoreConditional()) {
1321                     inst->setExecuted();
1322                     instToCommit(inst);
1338             if (inst->getFault() == NoFault) {
1339                 inst->execute();
1340                 if (!inst->readPredicate())
1341                     inst->forwardOldRegs();
1344             inst->setExecuted();
1346             instToCommit(inst);
1349         updateExeInstStats(inst);
1359         ThreadID tid = inst->threadNumber;
1363             toCommit->squashedSeqNum[tid] > inst->seqNum) {
1367             bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1369             if (inst->mispredicted() && !loadNotExecuted) {
1374                         tid,inst->seqNum);
1377                         tid,inst->seqNum,inst->readPredTarg());
1380                         tid,inst->seqNum,inst->pcState());
1382                 squashDueToBranch(inst, tid);
1384                 ppMispredict->notify(inst);
1386                 if (inst->readPredTaken()) {
1392                 assert(inst->isMemRef());
1400                         "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1402                         inst->pcState(), inst->seqNum, inst->physEffAddr);
1407                 instQueue.violation(inst, violator);
1418                 assert(inst->isMemRef());
1423                         "%s, inst PC: %s.  Addr is: %#x.\n",
1424                         violator->pcState(), inst->pcState(),
1425                         inst->physEffAddr);
1463         DynInstPtr inst = toCommit->insts[inst_num];
1464         ThreadID tid = inst->threadNumber;
1467                 inst->seqNum, inst->pcState());
1472         ppToCommit->notify(inst);
1479         if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1480             int dependents = instQueue.wakeDependents(inst);
1482             for (int i = 0; i < inst->numDestRegs(); i++) {
1484                 if (inst->renamedDestRegIdx(i)->
1487                             inst->renamedDestRegIdx(i)->index(),
1488                             inst->renamedDestRegIdx(i)->className());
1489                     scoreboard->setReg(inst->renamedDestRegIdx(i));
1634 DefaultIEW<Impl>::updateExeInstStats(const DynInstPtr& inst)
1636     ThreadID tid = inst->threadNumber;
1642         inst->completeTick = curTick() - inst->fetchTick;
1649     if (inst->isControl())
1655     if (inst->isMemRef()) {
1658         if (inst->isLoad()) {
1666 DefaultIEW<Impl>::checkMisprediction(const DynInstPtr& inst)
1668     ThreadID tid = inst->threadNumber;
1672         toCommit->squashedSeqNum[tid] > inst->seqNum) {
1674         if (inst->mispredicted()) {
1679                     tid,inst->seqNum);
1682                     tid,inst->seqNum,
1683                     inst->predInstAddr(), inst->predNextInstAddr());
1687                     tid,inst->seqNum,
1688                     inst->nextInstAddr(),
1689                     inst->nextInstAddr());
1691             squashDueToBranch(inst, tid);
1693             if (inst->readPredTaken()) {