Searched refs:icache (Results 1 - 25 of 29) sorted by relevance

12

/gem5/src/mem/ruby/system/
H A D	GPUCoalescer.py	51 icache = Param.RubyCache("") variable in class:RubyGPUCoalescer
H A D	Sequencer.py	64 icache = Param.RubyCache("") variable in class:RubySequencer
/gem5/util/tlm/conf/
H A D	tlm_elastic_slave.py	93 system.cpu.icache = L1_ICache(size="32kB") 95 system.cpu.icache.cpu_side = system.cpu.icache_port 115 system.cpu.icache.mem_side = system.membus.slave
/gem5/util/tlm/examples/
H A D	tlm_elastic_slave_with_l2.py	100 system.cpu.icache = L1_ICache(size="32kB") 102 system.cpu.icache.cpu_side = system.cpu.icache_port 123 system.cpu.icache.mem_side = system.tol2bus.slave
/gem5/configs/learning_gem5/part1/
H A D	two_level.py	99 system.cpu.icache = L1ICache(opts) 103 system.cpu.icache.connectCPU(system.cpu) 110 system.cpu.icache.connectBus(system.l2bus)
/gem5/configs/common/
H A D	CacheConfig.py	122 icache = icache_class(size=options.l1i_size, 162 if icache.prefetcher != m5.params.NULL: 165 "of type", type(icache.prefetcher), ", using the", 167 icache.prefetcher = hwpClass() 171 system.cpu[i].addPrivateSplitL1Caches(icache, dcache, 188 ExternalCache("cpu%d.icache" % i), 194 ExternalCache("cpu%d.icache" % i),
/gem5/configs/ruby/
H A D	Garnet_standalone.py	85 cpu_seq = RubySequencer(icache = cache,
H A D	AMD_Base_Constructor.py	84 self.sequencer.icache = self.L1Icache 92 self.sequencer1.icache = self.L1Icache
H A D	GPU_RfO.py	119 self.sequencer.icache = self.L1Icache 127 self.sequencer1.icache = self.L1Icache 133 # Defines icache/dcache hit latency 165 self.coalescer.icache = self.L1cache 176 self.sequencer.icache = self.L1cache 197 self.coalescer.icache = self.L1cache 205 self.sequencer.icache = self.L1cache 239 self.sequencer.icache = self.L1cache 260 self.sequencer.icache = self.L1cache
H A D	GPU_VIPER.py	105 self.sequencer.icache = self.L1Icache 113 self.sequencer1.icache = self.L1Icache 153 self.coalescer.icache = self.L1cache 161 self.sequencer.icache = self.L1cache 184 self.coalescer.icache = self.L1cache 192 self.sequencer.icache = self.L1cache 227 self.sequencer.icache = self.L1cache
H A D	GPU_VIPER_Region.py	106 self.sequencer.icache = self.L1Icache 114 self.sequencer1.icache = self.L1Icache 154 self.coalescer.icache = self.L1cache 162 self.sequencer.icache = self.L1cache 193 self.sequencer.icache = self.L1cache
H A D	GPU_VIPER_Baseline.py	105 self.sequencer.icache = self.L1Icache 113 self.sequencer1.icache = self.L1Icache 153 self.coalescer.icache = self.L1cache 161 self.sequencer.icache = self.L1cache 192 self.sequencer.icache = self.L1cache
H A D	MOESI_AMD_Base.py	106 self.sequencer.icache = self.L1Icache 114 self.sequencer1.icache = self.L1Icache 120 # Defines icache/dcache hit latency
H A D	MI_example.py	97 cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
H A D	MESI_Two_Level.py	107 cpu_seq = RubySequencer(version = i, icache = l1i_cache,
H A D	MOESI_CMP_directory.py	118 cpu_seq = RubySequencer(version=i, icache=l1i_cache,
H A D	MOESI_hammer.py	114 cpu_seq = RubySequencer(version=i, icache=l1i_cache,
H A D	MOESI_CMP_token.py	122 cpu_seq = RubySequencer(version=i, icache=l1i_cache,
H A D	MESI_Three_Level.py	118 icache = l0i_cache,
/gem5/configs/example/
H A D	ruby_gpu_random_test.py	67 sharing an SQC (icache, and thus icache TLB)")
/gem5/configs/learning_gem5/part3/
H A D	test_caches.py	80 icache = self.controllers[i].cacheMemory,
H A D	msi_caches.py	86 icache = self.controllers[i].cacheMemory,
H A D	ruby_caches_MI_example.py	86 icache = self.controllers[i].cacheMemory,
/gem5/src/arch/arm/
H A D	ArmPMU.py	104 icache=None, dcache=None,
/gem5/ext/mcpat/
H A D	core.h	106 CacheUnit* icache; member in class:InstFetchU

Completed in 35 milliseconds

12

Indexes created Thu Sep 26 06:36:22 EDT 2019