| /gem5/ext/mcpat/ |
| H A D | interconnect.h | 54 double accesses; member in class:InterconnectStatistics
111 double duty_cycle, double accesses);
|
| H A D | interconnect.cc | 181 set_pppm(pppm_t, int_stats.accesses, int_params.active_ports,
182 int_params.active_ports, int_stats.accesses);
198 double duty_cycle, double accesses) {
201 int_stats.accesses = accesses;
197 set_params_stats(double active_ports, double duty_cycle, double accesses) argument
|
| H A D | bus_interconnect.cc | 86 link_bus->int_stats.accesses = bus_stats.total_access;
|
| H A D | logic.h | 58 double accesses; member in class:selection_logic
|
| H A D | noc.cc | 169 link_bus->int_stats.accesses = noc_stats.total_access;
|
| H A D | logic.cc | 46 accesses(_accesses),
138 output_data.runtime_dynamic_energy = power.readOp.dynamic * accesses;
|
| /gem5/src/mem/cache/prefetch/ |
| H A D | sbooe.cc | 43 accesses(0)
91 accesses++;
93 return (accesses >= sandboxes.size());
|
| H A D | sbooe.hh | 69 * the fill in the cache for the latest N accesses which are used to
137 /** Number of accesses notified to the prefetcher */
138 unsigned int accesses; member in class:SBOOEPrefetcher
|
| /gem5/src/arch/mips/ |
| H A D | tlb.hh | 80 Stats::Formula accesses; member in class:MipsISA::TLB
|
| H A D | tlb.cc | 245 .desc("DTB read accesses")
261 .desc("DTB write accesses")
274 accesses
275 .name(name() + ".accesses")
276 .desc("DTB accesses")
281 accesses = read_accesses + write_accesses;
|
| /gem5/src/arch/riscv/ |
| H A D | tlb.hh | 79 Stats::Formula accesses; member in class:RiscvISA::TLB
|
| H A D | tlb.cc | 247 .desc("DTB read accesses")
263 .desc("DTB write accesses")
276 accesses
277 .name(name() + ".accesses")
278 .desc("DTB accesses")
283 accesses = read_accesses + write_accesses;
350 // unaligned memory accesses, this should only happen if the request's
|
| /gem5/src/arch/power/ |
| H A D | tlb.hh | 129 Stats::Formula accesses; member in class:PowerISA::TLB
|
| H A D | tlb.cc | 242 .desc("DTB read accesses")
258 .desc("DTB write accesses")
271 accesses
272 .name(name() + ".accesses")
273 .desc("DTB accesses")
278 accesses = read_accesses + write_accesses;
284 // Instruction accesses must be word-aligned
|
| /gem5/src/mem/cache/tags/ |
| H A D | fa_lru.hh | 106 * A fully associative LRU cache. Keeps statistics for accesses to a number of
385 /** Total number of accesses */
386 Stats::Scalar accesses; member in class:FALRU::CacheTracking
|
| H A D | fa_lru.cc | 416 accesses++;
444 accesses
446 .desc("The number of accesses to the FA LRU cache.")
|
| /gem5/src/arch/arm/ |
| H A D | tlb.hh | 192 Stats::Formula accesses; member in class:ArmISA::TLB
|
| H A D | tlb.cc | 457 .desc("ITB inst accesses")
472 .desc("DTB read accesses")
487 .desc("DTB write accesses")
500 accesses
501 .name(name() + ".accesses")
502 .desc("DTB accesses")
555 accesses = readAccesses + writeAccesses + instAccesses;
635 // Generate an alignment fault for unaligned data accesses to device or
821 // Generate an alignment fault for unaligned accesses to device or
1019 // 1) Instruction accesses
[all...] |
| /gem5/src/mem/cache/ |
| H A D | base.cc | 996 // As soon as the access arrives, for sequential accesses first access
997 // tags, then the data entry. In the case of parallel accesses the
1104 // outstanding accesses to a block, do the simple thing for
2007 accesses[access_idx]
2009 .desc("number of " + cstr + " accesses(hits+misses)")
2012 accesses[access_idx] = hits[access_idx] + misses[access_idx];
2015 accesses[access_idx].subname(i, system->getMasterName(i));
2021 .desc("number of demand (read+write) accesses")
2031 .desc("number of overall (read+write) accesses")
2046 .desc("miss rate for " + cstr + " accesses")
[all...] |
| H A D | base.hh | 360 * is an outstanding request that accesses the victim block) or
429 * Calculate latency of accesses that only touch the tag array.
720 * is called by both atomic and timing-mode accesses, and in atomic
795 * Write back dirty blocks in the cache using functional accesses.
924 /** Number of hits for demand accesses. */
926 /** Number of hit for all accesses. */
932 /** Number of misses for demand accesses. */
934 /** Number of misses for all accesses. */
947 /** The number of accesses per command and thread. */
948 Stats::Formula accesses[MemCm member in class:BaseCache
[all...] |