110234Syasuko.eckert@amd.com/***************************************************************************** 210234Syasuko.eckert@amd.com * McPAT 310234Syasuko.eckert@amd.com * SOFTWARE LICENSE AGREEMENT 410234Syasuko.eckert@amd.com * Copyright (c) 2010-2013 Advanced Micro Devices, Inc. 510234Syasuko.eckert@amd.com * All Rights Reserved 610234Syasuko.eckert@amd.com * 710234Syasuko.eckert@amd.com * Redistribution and use in source and binary forms, with or without 810234Syasuko.eckert@amd.com * modification, are permitted provided that the following conditions are 910234Syasuko.eckert@amd.com * met: redistributions of source code must retain the above copyright 1010234Syasuko.eckert@amd.com * notice, this list of conditions and the following disclaimer; 1110234Syasuko.eckert@amd.com * redistributions in binary form must reproduce the above copyright 1210234Syasuko.eckert@amd.com * notice, this list of conditions and the following disclaimer in the 1310234Syasuko.eckert@amd.com * documentation and/or other materials provided with the distribution; 1410234Syasuko.eckert@amd.com * neither the name of the copyright holders nor the names of its 1510234Syasuko.eckert@amd.com * contributors may be used to endorse or promote products derived from 1610234Syasuko.eckert@amd.com * this software without specific prior written permission. 1710234Syasuko.eckert@amd.com 1810234Syasuko.eckert@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1910234Syasuko.eckert@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2010234Syasuko.eckert@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2110234Syasuko.eckert@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2210234Syasuko.eckert@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2310234Syasuko.eckert@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2410234Syasuko.eckert@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2510234Syasuko.eckert@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2610234Syasuko.eckert@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2710234Syasuko.eckert@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2810234Syasuko.eckert@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2910234Syasuko.eckert@amd.com * 3010234Syasuko.eckert@amd.com * Author: Joel Hestness 3110234Syasuko.eckert@amd.com * 3210234Syasuko.eckert@amd.com ***************************************************************************/ 3310234Syasuko.eckert@amd.com 3410234Syasuko.eckert@amd.com#include <algorithm> 3510234Syasuko.eckert@amd.com#include <cassert> 3610234Syasuko.eckert@amd.com#include <cmath> 3710234Syasuko.eckert@amd.com#include <iostream> 3810234Syasuko.eckert@amd.com#include <string> 3910234Syasuko.eckert@amd.com 4010234Syasuko.eckert@amd.com#include "basic_circuit.h" 4110234Syasuko.eckert@amd.com#include "bus_interconnect.h" 4210234Syasuko.eckert@amd.com#include "common.h" 4310234Syasuko.eckert@amd.com#include "const.h" 4410234Syasuko.eckert@amd.com#include "io.h" 4510234Syasuko.eckert@amd.com#include "parameter.h" 4610234Syasuko.eckert@amd.com 4710234Syasuko.eckert@amd.comBusInterconnect::BusInterconnect(XMLNode* _xml_data, 4810234Syasuko.eckert@amd.com InputParameter* interface_ip_) 4910234Syasuko.eckert@amd.com : McPATComponent(_xml_data), link_bus(NULL), interface_ip(*interface_ip_) { 5010234Syasuko.eckert@amd.com name = "Bus Interconnect"; 5110234Syasuko.eckert@amd.com set_param_stats(); 5210234Syasuko.eckert@amd.com local_result = init_interface(&interface_ip, name); 5310234Syasuko.eckert@amd.com scktRatio = g_tp.sckt_co_eff; 5410234Syasuko.eckert@amd.com 5510234Syasuko.eckert@amd.com interface_ip.throughput = bus_params.link_throughput / bus_params.clockRate; 5610234Syasuko.eckert@amd.com interface_ip.latency = bus_params.link_latency / bus_params.clockRate; 5710234Syasuko.eckert@amd.com 5810234Syasuko.eckert@amd.com link_len /= bus_params.total_nodes; 5910234Syasuko.eckert@amd.com if (bus_params.total_nodes > 1) { 6010234Syasuko.eckert@amd.com //All links are shared by neighbors 6110234Syasuko.eckert@amd.com link_len /= 2; 6210234Syasuko.eckert@amd.com } 6310234Syasuko.eckert@amd.com 6410234Syasuko.eckert@amd.com link_bus = new Interconnect(xml_data, "Link", Uncore_device, 6510234Syasuko.eckert@amd.com bus_params.link_base_width, 6610234Syasuko.eckert@amd.com bus_params.link_base_height, 6710234Syasuko.eckert@amd.com bus_params.flit_size, link_len, &interface_ip, 6810234Syasuko.eckert@amd.com bus_params.link_start_wiring_level, 6910234Syasuko.eckert@amd.com bus_params.clockRate, 7010234Syasuko.eckert@amd.com bus_params.pipelinable, 7110234Syasuko.eckert@amd.com bus_params.route_over_perc); 7210234Syasuko.eckert@amd.com children.push_back(link_bus); 7310234Syasuko.eckert@amd.com} 7410234Syasuko.eckert@amd.com 7510234Syasuko.eckert@amd.comvoid BusInterconnect::computeEnergy() { 7610234Syasuko.eckert@amd.com // Initialize stats for TDP 7710234Syasuko.eckert@amd.com tdp_stats.reset(); 7810234Syasuko.eckert@amd.com tdp_stats.readAc.access = bus_stats.duty_cycle; 7910234Syasuko.eckert@amd.com link_bus->int_params.active_ports = bus_params.min_ports - 1; 8010234Syasuko.eckert@amd.com link_bus->int_stats.duty_cycle = 8110234Syasuko.eckert@amd.com bus_params.M_traffic_pattern * bus_stats.duty_cycle; 8210234Syasuko.eckert@amd.com 8310234Syasuko.eckert@amd.com // Initialize stats for runtime energy and power 8410234Syasuko.eckert@amd.com rtp_stats.reset(); 8510234Syasuko.eckert@amd.com rtp_stats.readAc.access = bus_stats.total_access; 8610234Syasuko.eckert@amd.com link_bus->int_stats.accesses = bus_stats.total_access; 8710234Syasuko.eckert@amd.com 8810234Syasuko.eckert@amd.com // Recursively compute energy 8910234Syasuko.eckert@amd.com McPATComponent::computeEnergy(); 9010234Syasuko.eckert@amd.com} 9110234Syasuko.eckert@amd.com 9210234Syasuko.eckert@amd.comvoid BusInterconnect::set_param_stats() { 9310234Syasuko.eckert@amd.com memset(&bus_params, 0, sizeof(BusInterconnectParameters)); 9410234Syasuko.eckert@amd.com 9510234Syasuko.eckert@amd.com int num_children = xml_data->nChildNode("param"); 9610234Syasuko.eckert@amd.com int i; 9710234Syasuko.eckert@amd.com int mat_type; 9810234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 9910234Syasuko.eckert@amd.com XMLNode* paramNode = xml_data->getChildNodePtr("param", &i); 10010234Syasuko.eckert@amd.com XMLCSTR node_name = paramNode->getAttribute("name"); 10110234Syasuko.eckert@amd.com XMLCSTR value = paramNode->getAttribute("value"); 10210234Syasuko.eckert@amd.com 10310234Syasuko.eckert@amd.com if (!node_name) 10410234Syasuko.eckert@amd.com warnMissingParamName(paramNode->getAttribute("id")); 10510234Syasuko.eckert@amd.com 10610234Syasuko.eckert@amd.com ASSIGN_FP_IF("clockrate", bus_params.clockRate); 10710234Syasuko.eckert@amd.com ASSIGN_INT_IF("flit_bits", bus_params.flit_size); 10810234Syasuko.eckert@amd.com ASSIGN_FP_IF("link_throughput", bus_params.link_throughput); 10910234Syasuko.eckert@amd.com ASSIGN_FP_IF("link_latency", bus_params.link_latency); 11010234Syasuko.eckert@amd.com ASSIGN_INT_IF("total_nodes", bus_params.total_nodes); 11110234Syasuko.eckert@amd.com ASSIGN_INT_IF("input_ports", bus_params.input_ports); 11210234Syasuko.eckert@amd.com ASSIGN_INT_IF("output_ports", bus_params.output_ports); 11310234Syasuko.eckert@amd.com ASSIGN_INT_IF("global_linked_ports", bus_params.global_linked_ports); 11410234Syasuko.eckert@amd.com ASSIGN_FP_IF("chip_coverage", bus_params.chip_coverage); 11510234Syasuko.eckert@amd.com ASSIGN_INT_IF("pipelinable", bus_params.pipelinable); 11610234Syasuko.eckert@amd.com ASSIGN_FP_IF("link_routing_over_percentage", 11710234Syasuko.eckert@amd.com bus_params.route_over_perc); 11810234Syasuko.eckert@amd.com ASSIGN_INT_IF("virtual_channel_per_port", 11910234Syasuko.eckert@amd.com bus_params.virtual_channel_per_port); 12010234Syasuko.eckert@amd.com ASSIGN_FP_IF("M_traffic_pattern", bus_params.M_traffic_pattern); 12110234Syasuko.eckert@amd.com ASSIGN_FP_IF("link_len", link_len); 12210234Syasuko.eckert@amd.com ASSIGN_FP_IF("link_base_width", bus_params.link_base_width); 12310234Syasuko.eckert@amd.com ASSIGN_FP_IF("link_base_height", bus_params.link_base_height); 12410234Syasuko.eckert@amd.com ASSIGN_FP_IF("link_start_wiring_level", 12510234Syasuko.eckert@amd.com bus_params.link_start_wiring_level); 12610234Syasuko.eckert@amd.com ASSIGN_INT_IF("wire_mat_type", mat_type); 12710234Syasuko.eckert@amd.com ASSIGN_ENUM_IF("wire_type", interface_ip.wt, Wire_type); 12810234Syasuko.eckert@amd.com 12910234Syasuko.eckert@amd.com else { 13010234Syasuko.eckert@amd.com warnUnrecognizedParam(node_name); 13110234Syasuko.eckert@amd.com } 13210234Syasuko.eckert@amd.com } 13310234Syasuko.eckert@amd.com 13410234Syasuko.eckert@amd.com // Change from MHz to Hz 13510234Syasuko.eckert@amd.com bus_params.clockRate *= 1e6; 13610234Syasuko.eckert@amd.com 13710234Syasuko.eckert@amd.com interface_ip.wire_is_mat_type = mat_type; 13810234Syasuko.eckert@amd.com interface_ip.wire_os_mat_type = mat_type; 13910234Syasuko.eckert@amd.com 14010234Syasuko.eckert@amd.com num_children = xml_data->nChildNode("stat"); 14110234Syasuko.eckert@amd.com for (i = 0; i < num_children; i++) { 14210234Syasuko.eckert@amd.com XMLNode* statNode = xml_data->getChildNodePtr("stat", &i); 14310234Syasuko.eckert@amd.com XMLCSTR node_name = statNode->getAttribute("name"); 14410234Syasuko.eckert@amd.com XMLCSTR value = statNode->getAttribute("value"); 14510234Syasuko.eckert@amd.com 14610234Syasuko.eckert@amd.com if (!node_name) 14710234Syasuko.eckert@amd.com warnMissingStatName(statNode->getAttribute("id")); 14810234Syasuko.eckert@amd.com 14910234Syasuko.eckert@amd.com ASSIGN_FP_IF("duty_cycle", bus_stats.duty_cycle); 15010234Syasuko.eckert@amd.com ASSIGN_FP_IF("total_accesses", bus_stats.total_access); 15110234Syasuko.eckert@amd.com 15210234Syasuko.eckert@amd.com else { 15310234Syasuko.eckert@amd.com warnUnrecognizedStat(node_name); 15410234Syasuko.eckert@amd.com } 15510234Syasuko.eckert@amd.com } 15610234Syasuko.eckert@amd.com 15710234Syasuko.eckert@amd.com clockRate = bus_params.clockRate; 15810234Syasuko.eckert@amd.com bus_params.min_ports = 15910234Syasuko.eckert@amd.com min(bus_params.input_ports, bus_params.output_ports); 16010234Syasuko.eckert@amd.com 16110234Syasuko.eckert@amd.com assert(bus_params.chip_coverage <= 1); 16210234Syasuko.eckert@amd.com assert(bus_params.route_over_perc <= 1); 16310234Syasuko.eckert@amd.com assert(link_len > 0); 16410234Syasuko.eckert@amd.com} 16510234Syasuko.eckert@amd.com 16610234Syasuko.eckert@amd.comvoid 16710234Syasuko.eckert@amd.comBusInterconnect::set_duty_cycle(double duty_cycle) { 16810234Syasuko.eckert@amd.com bus_stats.duty_cycle = duty_cycle; 16910234Syasuko.eckert@amd.com} 17010234Syasuko.eckert@amd.com 17110234Syasuko.eckert@amd.comvoid 17210234Syasuko.eckert@amd.comBusInterconnect::set_number_of_accesses(double total_accesses) { 17310234Syasuko.eckert@amd.com bus_stats.total_access = total_accesses; 17410234Syasuko.eckert@amd.com} 17510234Syasuko.eckert@amd.com 17610234Syasuko.eckert@amd.comBusInterconnect::~BusInterconnect() { 17710234Syasuko.eckert@amd.com delete link_bus; 17810234Syasuko.eckert@amd.com link_bus = NULL; 17910234Syasuko.eckert@amd.com} 180