| /gem5/ext/pybind11/tests/ |
| H A D | test_enum.py | 174 assert int(m.Flags.Write) == 2
176 assert int(m.Flags.Read | m.Flags.Write | m.Flags.Execute) == 7
177 assert int(m.Flags.Read | m.Flags.Write) == 6
179 assert int(m.Flags.Write | m.Flags.Execute) == 3
180 assert int(m.Flags.Write | 1) == 3
181 assert ~m.Flags.Write == -3
183 state = m.Flags.Read | m.Flags.Write
185 assert (state & m.Flags.Write) != 0
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| H A D | test_enum.cpp | 41 Write = 2, enumerator in enum:Flags
46 .value("Write", Flags::Write)
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| /gem5/src/cpu/ |
| H A D | translation.hh | 87 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
103 assert(mode == BaseTLB::Read || mode == BaseTLB::Write);
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| /gem5/src/arch/generic/ |
| H A D | tlb.hh | 59 enum Mode { Read, Write, Execute }; enumerator in enum:BaseTLB::Mode
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| /gem5/src/arch/x86/ |
| H A D | tlb.cc | 304 if (!attr.writable && (mode == Write || storeCheck))
394 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
404 return std::make_shared<PageFault>(vaddr, true, Write, inUser,
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| H A D | faults.hh | 328 code.write = (mode == BaseTLB::Write);
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| /gem5/src/arch/arm/ |
| H A D | isa.cc | 1675 mode = BaseTLB::Write;
1685 mode = BaseTLB::Write;
1699 mode = BaseTLB::Write;
1713 mode = BaseTLB::Write;
1723 mode = BaseTLB::Write;
1942 mode = BaseTLB::Write;
1952 mode = BaseTLB::Write;
1962 mode = BaseTLB::Write;
1972 mode = BaseTLB::Write;
1982 mode = BaseTLB::Write;
[all...] |
| H A D | semihosting.hh | 176 * Write data to file.
323 SEMI_CALL(Write);
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| H A D | tlb.cc | 578 bool is_write = (mode == Write);
616 bool is_write = (mode == Write);
803 bool is_write = !req->isCacheClean() && mode == Write;
1054 bool is_write = (mode == Write);
1462 bool is_write = (mode == Write);
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| /gem5/src/arch/mips/ |
| H A D | tlb.cc | 320 return translateData(req, tc, mode == Write);
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| /gem5/src/arch/power/ |
| H A D | tlb.cc | 321 return translateData(req, tc, mode == Write);
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| /gem5/src/cpu/checker/ |
| H A D | cpu.cc | 285 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
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| /gem5/src/cpu/simple/ |
| H A D | atomic.cc | 493 BaseTLB::Write);
603 BaseTLB::Write);
607 // We treat AMO accesses as Write accesses with SwapReq command
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| H A D | timing.cc | 508 BaseTLB::Mode mode = BaseTLB::Write;
576 BaseTLB::Mode mode = BaseTLB::Write;
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| /gem5/src/arch/riscv/ |
| H A D | tlb.cc | 373 return translateData(req, tc, mode == Write);
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| /gem5/src/gpu-compute/ |
| H A D | shader.cc | 241 trans_mode = BaseTLB::Write;
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| H A D | gpu_tlb.cc | 740 if (!attr.writable && (mode == BaseTLB::Write ||
843 if ((inUser && !entry->user) || (mode == BaseTLB::Write &&
856 BaseTLB::Write,
1139 (mode == BaseTLB::Write && badWrite)) {
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| H A D | compute_unit.cc | 760 // since atomic operations should use BaseTLB::Write
762 TLB_mode = BaseTLB::Write;
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| /gem5/src/arch/alpha/ |
| H A D | tlb.cc | 607 return translateData(req, tc, mode == Write);
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| /gem5/src/cpu/minor/ |
| H A D | lsq.cc | 310 request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write));
716 BaseTLB::Read : BaseTLB::Write));
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| /gem5/src/cpu/kvm/ |
| H A D | base.cc | 1128 BaseTLB::Mode tlb_mode(write ? BaseTLB::Write : BaseTLB::Read);
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| /gem5/ext/googletest/googletest/src/ |
| H A D | gtest-death-test.cc | 489 GTEST_DEATH_TEST_CHECK_SYSCALL_(posix::Write(write_fd(), &status_ch, 1));
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| /gem5/src/cpu/o3/ |
| H A D | lsq_impl.hh | 981 this->isLoad() ? BaseTLB::Read : BaseTLB::Write);
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| /gem5/ext/googletest/googletest/include/gtest/internal/ |
| H A D | gtest-port.h | 2360 // ChDir(), FReopen(), FDOpen(), Read(), Write(), Close(), and
2381 inline int Write(int fd, const void* buf, unsigned int count) { function in namespace:testing::internal::posix
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| /gem5/src/arch/sparc/ |
| H A D | tlb.cc | 842 return translateData(req, tc, mode == Write);
1063 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
|