Searched refs:Unsigned (Results 1 - 25 of 41) sorted by relevance

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/gem5/src/cpu/pred/
H A DBranchPredictor.py40 numThreads = Param.Unsigned(Parent.numThreads, "Number of threads")
49 indirectSets = Param.Unsigned(256, "Cache sets for indirect predictor")
50 indirectWays = Param.Unsigned(2, "Ways for indirect predictor")
51 indirectTagSize = Param.Unsigned(16, "Indirect target cache tag bits")
52 indirectPathLength = Param.Unsigned(3,
54 indirectGHRBits = Param.Unsigned(13, "Indirect GHR number of bits")
55 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
63 numThreads = Param.Unsigned(Parent.numThreads, "Number of threads")
64 BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
65 BTBTagSize = Param.Unsigned(1
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/gem5/src/cpu/o3/
H A DO3CPU.py77 activity = Param.Unsigned(0, "Initial count")
79 cacheStorePorts = Param.Unsigned(200, "Cache Ports. "
81 cacheLoadPorts = Param.Unsigned(200, "Cache Ports. "
89 fetchWidth = Param.Unsigned(8, "Fetch width")
90 fetchBufferSize = Param.Unsigned(64, "Fetch buffer size in bytes")
91 fetchQueueSize = Param.Unsigned(32, "Fetch queue size in micro-ops "
99 decodeWidth = Param.Unsigned(8, "Decode width")
105 renameWidth = Param.Unsigned(8, "Rename width")
113 dispatchWidth = Param.Unsigned(8, "Dispatch width")
114 issueWidth = Param.Unsigned(
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/gem5/src/dev/arm/
H A DSMMUv3.py53 port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
54 wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
55 xlate_slots = Param.Unsigned(16, 'Translation slots')
57 utlb_entries = Param.Unsigned(32, 'Micro TLB size (entries)')
58 utlb_assoc = Param.Unsigned(0, 'Micro TLB associativity (0=full)')
64 tlb_entries = Param.Unsigned(2048, 'Main TLB size (entries)')
65 tlb_assoc = Param.Unsigned(4, 'Main TLB associativity (0=full)')
95 xlate_slots = Param.Unsigned(64, 'SMMU translation slots')
96 ptw_slots = Param.Unsigned(16, 'SMMU page table walk slots')
98 master_port_width = Param.Unsigned(1
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H A DDisplay.py45 clock_frequency = Param.Unsigned("clock-frequency property")
46 hactive = Param.Unsigned("hactive property")
47 vactive = Param.Unsigned("vactive property")
48 hfront_porch = Param.Unsigned("hfront-porch property")
49 hback_porch = Param.Unsigned("hback-porch property")
50 hsync_len = Param.Unsigned("hsync-len property")
51 vfront_porch = Param.Unsigned("vfront-porch property")
52 vback_porch = Param.Unsigned("vback-porch property")
53 vsync_len = Param.Unsigned("vsync-len property")
/gem5/src/mem/probes/
H A DStackDistProbe.py51 line_size = Param.Unsigned(Parent.cache_line_size,
59 linear_hist_bins = Param.Unsigned('16', "Bins in linear histograms")
63 log_hist_bins = Param.Unsigned('32', "Bins in logarithmic histograms")
H A DMemFootprintProbe.py49 page_size = Param.Unsigned(4096, "Page size for page-level footprint")
/gem5/src/mem/
H A DSerialLink.py55 req_size = Param.Unsigned(16, "The number of requests to buffer")
56 resp_size = Param.Unsigned(16, "The number of responses to buffer")
62 num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
H A DBridge.py50 req_size = Param.Unsigned(16, "The number of requests to buffer")
51 resp_size = Param.Unsigned(16, "The number of responses to buffer")
H A DCommMonitor.py64 burst_length_bins = Param.Unsigned('20', "# bins in burst length " \
70 bandwidth_bins = Param.Unsigned('20', "# bins in bandwidth histograms")
74 latency_bins = Param.Unsigned('20', "# bins in latency histograms")
81 itt_bins = Param.Unsigned('20', "# bins in ITT distributions")
87 outstanding_bins = Param.Unsigned('20', "# bins in outstanding " \
93 transaction_bins = Param.Unsigned('20', "# bins in transaction " \
H A DDRAMCtrl.py85 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
86 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
97 min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
106 max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
120 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
122 burst_length = Param.Unsigned("Burst lenght (BL) in beats")
125 devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
126 ranks_per_channel = Param.Unsigned("Number of ranks per channel")
131 bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
132 banks_per_rank = Param.Unsigned("Numbe
[all...]
/gem5/src/cpu/trace/
H A DTraceCPU.py67 sizeStoreBuffer = Param.Unsigned(16, "Number of entries in the store "\
69 sizeLoadBuffer = Param.Unsigned(16, "Number of entries in the load buffer")
70 sizeROB = Param.Unsigned(40, "Number of entries in the re-order buffer")
87 progressMsgInterval = Param.Unsigned(0, "Interval of committed "\
/gem5/src/dev/virtio/
H A DVirtIOConsole.py49 qRecvSize = Param.Unsigned(16, "Receive queue size (descriptors)")
50 qTransSize = Param.Unsigned(16, "Transmit queue size (descriptors)")
H A DVirtIOBlock.py48 queueSize = Param.Unsigned(128, "Output queue size (pages)")
H A DVirtIO9P.py49 queueSize = Param.Unsigned(32, "Output queue size (pages)")
/gem5/src/mem/qos/
H A DQoSMemSinkCtrl.py51 write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
52 read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
/gem5/src/cpu/minor/
H A DMinorCPU.py118 cantForwardFromFUIndices = VectorParam.Unsigned([],
206 fetch1FetchLimit = Param.Unsigned(1,
208 fetch1LineSnapWidth = Param.Unsigned(0,
211 fetch1LineWidth = Param.Unsigned(0,
220 fetch2InputBufferSize = Param.Unsigned(2,
228 decodeInputBufferSize = Param.Unsigned(3,
232 decodeInputWidth = Param.Unsigned(2,
239 executeInputWidth = Param.Unsigned(2,
244 executeIssueLimit = Param.Unsigned(2,
246 executeMemoryIssueLimit = Param.Unsigned(
[all...]
/gem5/src/arch/x86/
H A DX86TLB.py50 num_squash_per_cycle = Param.Unsigned(4,
57 size = Param.Unsigned(64, "TLB size")
/gem5/src/mem/cache/
H A DCache.py63 coalesce_limit = Param.Unsigned(2, "Consecutive lines written before "
65 no_allocate_limit = Param.Unsigned(12, "Consecutive lines written before"
68 delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an "
81 assoc = Param.Unsigned("Associativity")
93 mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
94 demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
95 tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
96 write_buffers = Param.Unsigned(8, "Number of write buffers")
/gem5/src/mem/cache/prefetch/
H A DPrefetcher.py180 pt_table_assoc = Param.Unsigned(16, "Associativity of the Prefetch Table")
187 max_prefetch_distance = Param.Unsigned(16, "Maximum prefetch distance")
188 num_indirect_counter_bits = Param.Unsigned(3,
192 ipd_table_assoc = Param.Unsigned(4,
201 addr_array_len = Param.Unsigned(4, "Number of misses tracked")
202 prefetch_threshold = Param.Unsigned(2,
204 stream_counter_threshold = Param.Unsigned(4,
206 streaming_distance = Param.Unsigned(4,
220 signature_table_assoc = Param.Unsigned(2,
233 pattern_table_assoc = Param.Unsigned(
[all...]
/gem5/src/cpu/o3/probe/
H A DElasticTrace.py54 depWindowSize = Param.Unsigned(desc="Instruction window size used for " \
/gem5/src/cpu/testers/traffic_gen/
H A DBaseTrafficGen.py91 sids = VectorParam.Unsigned([], "StreamIDs to use")
92 ssids = VectorParam.Unsigned([], "SubstreamIDs to use")
97 socket_id = Param.Unsigned(0, "Physical Socket identifier")
98 numThreads = Param.Unsigned(1, "number of HW thread contexts")
/gem5/src/sim/
H A DClockDomain.py81 clk_divider = Param.Unsigned(1, "Frequency divider")
H A DClockedObject.py78 p_state_clk_gate_bins = Param.Unsigned('20',
/gem5/src/mem/ruby/network/
H A DMessageBuffer.py38 buffer_size = Param.Unsigned(0, "Maximum number of entries to buffer \
/gem5/src/base/filters/
H A DBloomFilters.py42 offset_bits = Param.Unsigned(6, "Number of bits in a cache line offset")
53 masks_lsbs = VectorParam.Unsigned([Self.offset_bits,
55 masks_sizes = VectorParam.Unsigned([Self.offset_bits, Self.offset_bits],

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