1# Copyright (c) 2013 - 2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Radhika Jagtap 37# Andreas Hansson 38# Thomas Grass 39 40from m5.params import * 41from m5.objects.BaseCPU import BaseCPU 42 43class TraceCPU(BaseCPU): 44 """Trace CPU model which replays traces generated in a prior simulation 45 using DerivO3CPU or its derived classes. It interfaces with L1 caches. 46 """ 47 type = 'TraceCPU' 48 cxx_header = "cpu/trace/trace_cpu.hh" 49 50 @classmethod 51 def memory_mode(cls): 52 return 'timing' 53 54 @classmethod 55 def require_caches(cls): 56 return True 57 58 def addPMU(self, pmu = None): 59 pass 60 61 @classmethod 62 def support_take_over(cls): 63 return True 64 65 instTraceFile = Param.String("", "Instruction trace file") 66 dataTraceFile = Param.String("", "Data dependency trace file") 67 sizeStoreBuffer = Param.Unsigned(16, "Number of entries in the store "\ 68 "buffer") 69 sizeLoadBuffer = Param.Unsigned(16, "Number of entries in the load buffer") 70 sizeROB = Param.Unsigned(40, "Number of entries in the re-order buffer") 71 72 # Frequency multiplier used to effectively scale the Trace CPU frequency 73 # either up or down. Note that the Trace CPU's clock domain must also be 74 # changed when frequency is scaled. A default value of 1.0 means the same 75 # frequency as was used for generating the traces. 76 freqMultiplier = Param.Float(1.0, "Multiplier scale the Trace CPU "\ 77 "frequency up or down") 78 79 # Enable exiting when any one Trace CPU completes execution which is set to 80 # false by default 81 enableEarlyExit = Param.Bool(False, "Exit when any one Trace CPU "\ 82 "completes execution") 83 84 # If progress msg interval is set to a non-zero value, it is treated as 85 # the interval of committed instructions at which an info message is 86 # printed. 87 progressMsgInterval = Param.Unsigned(0, "Interval of committed "\ 88 "instructions at which to print a"\ 89 " progress msg") 90