dev/arm/SMMUv3.py

53     port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
54     wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
55     xlate_slots = Param.Unsigned(16, 'Translation slots')
57     utlb_entries = Param.Unsigned(32, 'Micro TLB size (entries)')
58     utlb_assoc = Param.Unsigned(0, 'Micro TLB associativity (0=full)')
64     tlb_entries = Param.Unsigned(2048, 'Main TLB size (entries)')
65     tlb_assoc = Param.Unsigned(4, 'Main TLB associativity (0=full)')
95     xlate_slots = Param.Unsigned(64, 'SMMU translation slots')
96     ptw_slots = Param.Unsigned(16, 'SMMU page table walk slots')
98     master_port_width = Param.Unsigned(16,
101     tlb_entries = Param.Unsigned(2048, 'TLB size (entries)')
102     tlb_assoc = Param.Unsigned(4, 'TLB associativity (0=full)')
108     cfg_entries = Param.Unsigned(64, 'Config cache size (entries)')
109     cfg_assoc = Param.Unsigned(4, 'Config cache associativity (0=full)')
115     ipa_entries = Param.Unsigned(128, 'IPA cache size (entries)')
116     ipa_assoc = Param.Unsigned(4, 'IPA cache associativity (0=full)')
122     walk_S1L0 = Param.Unsigned(4, 'Walk cache S1L0 size (entries)')
123     walk_S1L1 = Param.Unsigned(28, 'Walk cache S1L1 size (entries)')
124     walk_S1L2 = Param.Unsigned(348, 'Walk cache S1L2 size (entries)')
125     walk_S1L3 = Param.Unsigned(4, 'Walk cache S1L3 size (entries)')
126     walk_S2L0 = Param.Unsigned(4, 'Walk cache S2L0 size (entries)')
127     walk_S2L1 = Param.Unsigned(28, 'Walk cache S2L1 size (entries)')
128     walk_S2L2 = Param.Unsigned(92, 'Walk cache S2L2 size (entries)')
129     walk_S2L3 = Param.Unsigned(4, 'Walk cache S2L3 size (entries)')
130     walk_assoc = Param.Unsigned(4, 'Walk cache associativity (0=full)')
135     wc_s1_levels = Param.Unsigned(7,
137     wc_s2_levels = Param.Unsigned(7,