Searched refs:RegId (Results 1 - 25 of 48) sorted by relevance

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/gem5/src/cpu/
H A Dreg_class.cc45 const char *RegId::regClassStrings[] = {
H A Dreg_class.hh79 class RegId { class
88 friend struct std::hash<RegId>;
91 RegId() : RegId(IntRegClass, 0) {} function in class:RegId
93 RegId(RegClass reg_class, RegIndex reg_idx) function in class:RegId
94 : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {}
96 explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx) function in class:RegId
108 bool operator==(const RegId& that) const {
113 bool operator!=(const RegId& that) const {
118 * The order is required to implement maps with key type RegId
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H A Dthread_context.hh213 virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
214 virtual VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
220 readVec8BitLaneReg(const RegId& reg) const = 0;
224 readVec16BitLaneReg(const RegId& reg) const = 0;
228 readVec32BitLaneReg(const RegId& reg) const = 0;
232 readVec64BitLaneReg(const RegId& reg) const = 0;
235 virtual void setVecLane(const RegId& reg,
237 virtual void setVecLane(const RegId& reg,
239 virtual void setVecLane(const RegId& reg,
241 virtual void setVecLane(const RegId
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H A Dsimple_thread.hh307 readVecReg(const RegId& reg) const override
318 getWritableVecReg(const RegId& reg) override
333 readVecLane(const RegId& reg) const
345 readVec8BitLaneReg(const RegId &reg) const override
352 readVec16BitLaneReg(const RegId &reg) const override
359 readVec32BitLaneReg(const RegId &reg) const override
366 readVec64BitLaneReg(const RegId &reg) const override
374 setVecLaneT(const RegId &reg, const LD &val)
383 setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
388 setVecLane(const RegId
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/gem5/src/arch/x86/
H A Disa.hh73 RegId
74 flattenRegId(const RegId& regId) const
78 return RegId(IntRegClass, flattenIntIndex(regId.index()));
80 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
82 return RegId(CCRegClass, flattenCCIndex(regId.index()));
84 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
/gem5/src/cpu/o3/
H A Dthread_context.hh193 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
199 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
206 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
211 readVecReg(const RegId& id) const override
220 getWritableVecReg(const RegId& id) override
229 readVec8BitLaneReg(const RegId& id) const override
237 readVec16BitLaneReg(const RegId& id) const override
245 readVec32BitLaneReg(const RegId& id) const override
253 readVec64BitLaneReg(const RegId& id) const override
261 setVecLane(const RegId
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H A Drename_map.hh90 RegId zeroReg;
120 RenameInfo rename(const RegId& arch_reg);
127 PhysRegIdPtr lookup(const RegId& arch_reg) const
139 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
224 * RegId and reads the appropriate class-specific rename table.
229 RenameInfo rename(const RegId& arch_reg)
268 PhysRegIdPtr lookup(const RegId& arch_reg) const
310 void setEntry(const RegId& arch_reg, PhysRegIdPtr phys_reg)
H A Drename_map.cc70 zeroReg = RegId(IntRegClass, _zeroReg);
74 SimpleRenameMap::rename(const RegId& arch_reg)
190 setEntry(RegId(VecElemClass, vec_idx, idx), &(*phys_elem));
209 RegId s_rid(VecElemClass, i, l);
H A Dcpu.cc248 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
249 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
254 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
256 RegId(FloatRegClass, ridx), phys_reg);
265 RegId rid = RegId(VecRegClass, ridx);
275 RegId lrid = RegId(VecElemClass, ridx, ldx);
285 renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg);
287 RegId(VecPredRegClas
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/gem5/src/arch/power/
H A Disa.hh90 RegId flattenRegId(const RegId& regId) const { return regId; }
/gem5/src/arch/riscv/
H A Disa.hh82 RegId flattenRegId(const RegId &regId) const { return regId; }
/gem5/src/cpu/minor/
H A Dexec_context.hh146 const RegId& reg = si->srcRegIdx(idx);
154 const RegId& reg = si->srcRegIdx(idx);
162 const RegId& reg = si->srcRegIdx(idx);
170 const RegId& reg = si->destRegIdx(idx);
178 const RegId& reg = si->srcRegIdx(idx);
186 const RegId& reg = si->srcRegIdx(idx);
194 const RegId& reg = si->destRegIdx(idx);
202 const RegId& reg = si->destRegIdx(idx);
210 const RegId& reg = si->destRegIdx(idx);
219 const RegId
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H A Dscoreboard.cc51 Scoreboard::findIndex(const RegId& reg, Index &scoreboard_index)
102 /** Flatten a RegId, irrespective of what reg type it's pointing to */
103 static RegId
104 flattenRegIndex(const RegId& reg, ThreadContext *thread_context)
123 RegId reg = flattenRegIndex(
147 inst->flatDestRegIdx[dest_index] = RegId(IntRegClass,
166 RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
195 const RegId& reg = inst->flatDestRegIdx[dest_index];
252 RegId reg = flattenRegIndex(staticInst->srcRegIdx(src_index),
/gem5/src/cpu/checker/
H A Dthread_context.hh251 readVecReg (const RegId &reg) const override
260 getWritableVecReg (const RegId &reg) override
269 readVec8BitLaneReg(const RegId &reg) const override
276 readVec16BitLaneReg(const RegId &reg) const override
283 readVec32BitLaneReg(const RegId &reg) const override
290 readVec64BitLaneReg(const RegId &reg) const override
297 setVecLane(const RegId &reg,
303 setVecLane(const RegId &reg,
309 setVecLane(const RegId &reg,
315 setVecLane(const RegId
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H A Dcpu.hh194 const RegId& reg = si->srcRegIdx(idx);
202 const RegId& reg = si->srcRegIdx(idx);
213 const RegId& reg = si->srcRegIdx(idx);
224 const RegId& reg = si->destRegIdx(idx);
235 const RegId& reg = si->destRegIdx(idx);
244 const RegId& reg = si->destRegIdx(idx);
253 const RegId& reg = si->destRegIdx(idx);
262 const RegId& reg = si->destRegIdx(idx);
272 const RegId& reg = si->destRegIdx(idx);
305 const RegId
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/gem5/src/cpu/simple/
H A Dexec_context.hh181 const RegId& reg = si->srcRegIdx(idx);
191 const RegId& reg = si->destRegIdx(idx);
202 const RegId& reg = si->srcRegIdx(idx);
213 const RegId& reg = si->destRegIdx(idx);
223 const RegId& reg = si->srcRegIdx(idx);
233 const RegId& reg = si->destRegIdx(idx);
244 const RegId& reg = si->destRegIdx(idx);
257 const RegId& reg = si->srcRegIdx(idx);
292 const RegId& reg = si->destRegIdx(idx);
323 const RegId
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/gem5/src/arch/mips/
H A Dmt.hh56 readRegOtherThread(ThreadContext *tc, const RegId &reg,
80 setRegOtherThread(ThreadContext *tc, const RegId& reg, RegVal val,
104 readRegOtherThread(ExecContext *xc, const RegId &reg,
111 setRegOtherThread(ExecContext *xc, const RegId& reg, RegVal val,
179 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_BIND), tid);
185 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_STATUS),
189 readRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_HALT),
195 setRegOtherThread(tc, RegId(MiscRegClass, MISCREG_TC_RESTART),
197 setRegOtherThread(tc, RegId(IntRegClass, Rd_bits), Rt, tid);
216 setRegOtherThread(tc, RegId(MiscRegClas
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H A Disa.hh141 RegId flattenRegId(const RegId& regId) const { return regId; }
/gem5/src/arch/sparc/
H A Disa.hh192 RegId
193 flattenRegId(const RegId& regId) const
197 return RegId(IntRegClass, flattenIntIndex(regId.index()));
199 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
201 return RegId(CCRegClass, flattenCCIndex(regId.index()));
203 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
/gem5/src/arch/power/insts/
H A Dstatic_inst.cc39 PowerStaticInst::printReg(std::ostream &os, RegId reg) const
H A Dstatic_inst.hh62 printReg(std::ostream &os, RegId reg) const;
/gem5/src/arch/alpha/
H A Disa.hh98 RegId flattenRegId(const RegId& regId) const { return regId; }
/gem5/src/arch/x86/insts/
H A Dstatic_inst.hh54 struct InstRegIndex : public RegId
57 RegId(computeRegClass(_idx), _idx) {}
100 void printReg(std::ostream &os, RegId reg, int size) const;
/gem5/src/arch/sparc/insts/
H A Dstatic_inst.hh97 static void printReg(std::ostream &os, RegId reg);
103 const RegId indexArray[], int num) const;
/gem5/src/arch/arm/tracers/
H A Dtarmac_record.hh121 TraceRegEntry(const TarmacContext& tarmCtx, const RegId& reg);
208 genRegister(const TarmacContext& tarmCtx, const RegId& reg)
243 RegId reg(MiscRegClass, ArmISA::MISCREG_CPSR);

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