Searched refs:NumIntArchRegs (Results 1 - 18 of 18) sorted by relevance

/gem5/src/arch/power/
H A Dregisters.hh65 const int NumIntArchRegs = 32; member in namespace:PowerISA
74 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
101 INTREG_CR = NumIntArchRegs,
H A Dremote_gdb.hh58 uint32_t gpr[NumIntArchRegs];
H A Dremote_gdb.cc183 for (int i = 0; i < NumIntArchRegs; i++)
202 for (int i = 0; i < NumIntArchRegs; i++)
/gem5/src/arch/sparc/
H A Dnativetrace.cc41 static const char *intRegNames[SparcISA::NumIntArchRegs] = {
62 assert(SparcISA::NumIntArchRegs == 32);
64 for (int i = 0; i < SparcISA::NumIntArchRegs; i++) {
87 regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2);
H A Dprocess.cc130 tc->setIntReg(NumIntArchRegs + 6, 0);
133 tc->setIntReg(NumIntArchRegs + 4, 0);
136 tc->setIntReg(NumIntArchRegs + 3, NWindows - 2);
139 tc->setIntReg(NumIntArchRegs + 5, NWindows);
144 tc->setIntReg(NumIntArchRegs + 7, 0);
438 RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
439 RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
440 RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
465 tc->setIntReg(NumIntArchRegs + 3, Cansave);
466 tc->setIntReg(NumIntArchRegs
[all...]
H A Dregisters.hh75 const int NumIntArchRegs = 32; member in namespace:SparcISA
H A Dremote_gdb.cc182 r.y = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 1));
186 r.csr = htobe((uint32_t)context->readIntReg(NumIntArchRegs + 2));
200 r.y = htobe(context->readIntReg(NumIntArchRegs + 1));
206 context->readIntReg(NumIntArchRegs + 2) << 32);
H A Dutility.cc225 for (int y = NumIntArchRegs; y < NumIntArchRegs + NumMicroIntRegs; ++y)
H A Dfaults.cc309 RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
312 RegVal CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
388 RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
391 RegVal CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
/gem5/src/arch/x86/
H A Dregisters.hh59 const int NumIntArchRegs = NUM_INTREGS; member in namespace:X86ISA
60 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
/gem5/src/arch/riscv/
H A Dremote_gdb.cc167 for (int i = 0; i < NumIntArchRegs; i++)
176 for (int i = 0; i < NumIntArchRegs; i++)
H A Dremote_gdb.hh65 uint64_t gpr[NumIntArchRegs];
H A Dutility.hh140 if (reg.index() >= NumIntArchRegs) {
H A Dregisters.hh87 const int NumIntArchRegs = 32; member in namespace:RiscvISA
89 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
/gem5/src/arch/alpha/
H A Dregisters.hh89 const int NumIntArchRegs = 32; member in namespace:AlphaISA
93 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs;
/gem5/src/arch/mips/
H A Dregisters.hh51 const int NumIntArchRegs = 32; member in namespace:MipsISA
57 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs
92 INTREG_LO = NumIntArchRegs,
/gem5/src/arch/sparc/linux/
H A Dlinux.hh194 ctc->setIntReg(SparcISA::NumIntArchRegs + 6, 0);
195 ctc->setIntReg(SparcISA::NumIntArchRegs + 4, 0);
196 ctc->setIntReg(SparcISA::NumIntArchRegs + 3, SparcISA::NWindows - 2);
197 ctc->setIntReg(SparcISA::NumIntArchRegs + 5, SparcISA::NWindows);
199 ctc->setIntReg(SparcISA::NumIntArchRegs + 7, 0);
/gem5/src/arch/arm/
H A Dregisters.hh82 const int NumIntArchRegs = NUM_ARCH_INTREGS; member in namespace:ArmISA

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