Searched refs:BaseCPU (Results 1 - 25 of 73) sorted by relevance
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| /gem5/src/arch/null/ |
| H A D | cpu_dummy.hh | 45 class BaseCPU class
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| /gem5/src/cpu/ |
| H A D | CheckerCPU.py | 31 from m5.objects.BaseCPU import BaseCPU
33 class CheckerCPU(BaseCPU):
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| H A D | base.cc | 67 #include "params/BaseCPU.hh"
80 vector<BaseCPU *> BaseCPU::cpuList;
87 CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
128 BaseCPU::BaseCPU(Params *p, bool is_checker) function in class:BaseCPU
268 BaseCPU::enableFunctionTrace()
273 BaseCPU::~BaseCPU()
281 BaseCPU
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| H A D | intr_control.cc | 54 BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
63 BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
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| H A D | base.hh | 70 class BaseCPU;
93 BaseCPU *cpu;
97 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
109 class BaseCPU : public ClockedObject class in inherits:ClockedObject
119 // takeover (which should be done from within the BaseCPU anyway,
313 BaseCPU(Params *params, bool is_checker = false);
314 virtual ~BaseCPU();
349 virtual void takeOverFrom(BaseCPU *cpu);
598 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
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| H A D | thread_state.hh | 62 ThreadState(BaseCPU *cpu, ThreadID _tid, Process *_process);
166 BaseCPU *baseCpu;
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| /gem5/src/arch/power/ |
| H A D | interrupts.hh | 38 class BaseCPU;
46 BaseCPU * cpu;
61 setCPU(BaseCPU * _cpu)
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| /gem5/src/cpu/kvm/ |
| H A D | BaseKvmCPU.py | 42 from m5.objects.BaseCPU import BaseCPU
45 class BaseKvmCPU(BaseCPU):
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| /gem5/src/cpu/trace/ |
| H A D | TraceCPU.py | 41 from m5.objects.BaseCPU import BaseCPU
43 class TraceCPU(BaseCPU):
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| /gem5/src/cpu/simple/ |
| H A D | BaseSimpleCPU.py | 34 from m5.objects.BaseCPU import BaseCPU
38 class BaseSimpleCPU(BaseCPU):
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| /gem5/src/dev/alpha/ |
| H A D | backdoor.hh | 44 class BaseCPU;
98 BaseCPU *cpu;
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| H A D | AlphaBackdoor.py | 38 cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
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| /gem5/src/arch/mips/ |
| H A D | interrupts.hh | 43 class BaseCPU;
65 setCPU(BaseCPU *_cpu)
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| H A D | isa.hh | 44 class BaseCPU;
120 void processCP0Event(BaseCPU *cpu, CP0EventType);
123 void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
127 void updateCPU(BaseCPU *cpu);
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| /gem5/src/cpu/minor/ |
| H A D | stats.hh | 86 void regStats(const std::string &name, BaseCPU &baseCpu);
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| H A D | cpu.cc | 51 BaseCPU(params),
96 BaseCPU::init();
124 /** Stats interface from SimObject (by way of BaseCPU) */
128 BaseCPU::regStats();
149 BaseCPU::serialize(cp);
156 BaseCPU::unserialize(cp);
184 BaseCPU::startup();
265 BaseCPU::switchOut();
272 MinorCPU::takeOverFrom(BaseCPU *old_cpu)
276 BaseCPU
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| H A D | stats.cc | 49 MinorStats::regStats(const std::string &name, BaseCPU &baseCpu)
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| H A D | cpu.hh | 79 class MinorCPU : public BaseCPU
138 /** Stats interface from SimObject (by way of BaseCPU) */
141 /** Simple inst count interface from BaseCPU */
160 /** Switching interface from BaseCPU */
162 void takeOverFrom(BaseCPU *old_cpu) override;
164 /** Thread activation interface from BaseCPU. */
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| H A D | MinorCPU.py | 49 from m5.objects.BaseCPU import BaseCPU
188 class MinorCPU(BaseCPU):
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| /gem5/src/gpu-compute/ |
| H A D | dispatcher.hh | 52 class BaseCPU;
84 BaseCPU *cpu;
110 void accessUserVar(BaseCPU *cpu, uint64_t addr, int val, int off);
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| H A D | shader.hh | 100 BaseCPU *cpuPointer;
198 void hostWakeUp(BaseCPU *cpu);
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| /gem5/src/arch/riscv/ |
| H A D | interrupts.hh | 45 class BaseCPU;
57 BaseCPU * cpu;
72 void setCPU(BaseCPU * _cpu) { cpu = _cpu; }
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| /gem5/src/cpu/o3/ |
| H A D | O3CPU.py | 47 from m5.objects.BaseCPU import BaseCPU
61 class DerivO3CPU(BaseCPU):
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| /gem5/src/arch/x86/ |
| H A D | interrupts.hh | 67 class BaseCPU;
170 BaseCPU *cpu;
189 void setCPU(BaseCPU * newCPU);
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| /gem5/util/cxx_config/ |
| H A D | main.cc | 281 BaseCPU &old_cpu = config_manager->getObject<BaseCPU>(from_cpu);
282 BaseCPU &new_cpu = config_manager->getObject<BaseCPU>(to_cpu);
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