1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40#include "cpu/minor/stats.hh"
41
42namespace Minor
43{
44
45MinorStats::MinorStats()
46{ }
47
48void
49MinorStats::regStats(const std::string &name, BaseCPU &baseCpu)
50{
51    numInsts
52        .name(name + ".committedInsts")
53        .desc("Number of instructions committed");
54
55    numOps
56        .name(name + ".committedOps")
57        .desc("Number of ops (including micro ops) committed");
58
59    numDiscardedOps
60        .name(name + ".discardedOps")
61        .desc("Number of ops (including micro ops) which were discarded "
62            "before commit");
63
64    numFetchSuspends
65        .name(name + ".numFetchSuspends")
66        .desc("Number of times Execute suspended instruction fetching");
67
68    quiesceCycles
69        .name(name + ".quiesceCycles")
70        .desc("Total number of cycles that CPU has spent quiesced or waiting "
71              "for an interrupt")
72        .prereq(quiesceCycles);
73
74    cpi
75        .name(name + ".cpi")
76        .desc("CPI: cycles per instruction")
77        .precision(6);
78    cpi = baseCpu.numCycles / numInsts;
79
80    ipc
81        .name(name + ".ipc")
82        .desc("IPC: instructions per cycle")
83        .precision(6);
84    ipc = numInsts / baseCpu.numCycles;
85
86    committedInstType
87        .init(baseCpu.numThreads, Enums::Num_OpClass)
88        .name(name + ".op_class")
89        .desc("Class of committed instruction")
90        .flags(Stats::total | Stats::pdf | Stats::dist);
91    committedInstType.ysubnames(Enums::OpClassStrings);
92}
93
94};
95