1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andrew Bardsley
38 */
39
40/**
41 * @file
42 *
43 * The stats for MinorCPU separated from the CPU definition.
44 */
45
46#ifndef __CPU_MINOR_STATS_HH__
47#define __CPU_MINOR_STATS_HH__
48
49#include "base/statistics.hh"
50#include "cpu/base.hh"
51#include "sim/ticked_object.hh"
52
53namespace Minor
54{
55
56/** Currently unused stats class. */
57class MinorStats
58{
59  public:
60    /** Number of simulated instructions */
61    Stats::Scalar numInsts;
62
63    /** Number of simulated insts and microops */
64    Stats::Scalar numOps;
65
66    /** Number of ops discarded before committing */
67    Stats::Scalar numDiscardedOps;
68
69    /** Number of times fetch was asked to suspend by Execute */
70    Stats::Scalar numFetchSuspends;
71
72    /** Number of cycles in quiescent state */
73    Stats::Scalar quiesceCycles;
74
75    /** CPI/IPC for total cycle counts and macro insts */
76    Stats::Formula cpi;
77    Stats::Formula ipc;
78
79    /** Number of instructions by type (OpClass) */
80    Stats::Vector2d committedInstType;
81
82  public:
83    MinorStats();
84
85  public:
86    void regStats(const std::string &name, BaseCPU &baseCpu);
87};
88
89}
90
91#endif /* __CPU_MINOR_STATS_HH__ */
92