| /gem5/src/arch/x86/linux/ |
| H A D | linux.hh | 58 ctc->setMiscRegNoEffect(X86ISA::MISCREG_FS_BASE, tls);
59 ctc->setMiscRegNoEffect(X86ISA::MISCREG_FS_EFF_BASE, tls);
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| H A D | process.cc | 133 tc->setMiscRegNoEffect(MISCREG_FS_BASE, addr);
134 tc->setMiscRegNoEffect(MISCREG_FS_EFF_BASE, addr);
141 tc->setMiscRegNoEffect(MISCREG_GS_BASE, addr);
142 tc->setMiscRegNoEffect(MISCREG_GS_EFF_BASE, addr);
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| /gem5/src/arch/riscv/ |
| H A D | process.cc | 105 system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
115 system->getThreadContext(ctx)->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
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| /gem5/src/cpu/o3/ |
| H A D | thread_context_impl.hh | 346 O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val) function in class:O3ThreadContext
348 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
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| H A D | thread_context.hh | 399 void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override;
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| H A D | cpu.hh | 348 void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid);
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| H A D | cpu.cc | 1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) function in class:FullO3CPU
1186 this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
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| /gem5/src/arch/arm/kvm/ |
| H A D | armv8_cpu.cc | 289 tc->setMiscRegNoEffect(MISCREG_CPSR, cpsr);
302 tc->setMiscRegNoEffect(ri.idx, value);
342 tc->setMiscRegNoEffect(ri.idx, value);
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| H A D | arm_cpu.cc | 737 tc->setMiscRegNoEffect(ri->idx, getOneRegU32(ri->id));
799 tc->setMiscRegNoEffect(
806 tc->setMiscRegNoEffect(reg, value);
820 tc->setMiscRegNoEffect(reg, getOneRegU32(id));
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| /gem5/src/cpu/checker/ |
| H A D | thread_context.hh | 437 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
441 checkerTC->setMiscRegNoEffect(misc_reg, val);
442 actualTC->setMiscRegNoEffect(misc_reg, val);
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| H A D | cpu.hh | 467 setMiscRegNoEffect(int misc_reg, RegVal val) function in class:CheckerCPU
472 return thread->setMiscRegNoEffect(misc_reg, val);
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| /gem5/src/arch/sparc/ |
| H A D | isa.hh | 189 void setMiscRegNoEffect(int miscReg, RegVal val);
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| H A D | isa.cc | 386 ISA::setMiscRegNoEffect(int miscReg, RegVal val) function in class:SparcISA::ISA
639 setMiscRegNoEffect(miscReg, new_val);
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| /gem5/src/arch/mips/ |
| H A D | utility.cc | 257 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
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| H A D | mt.hh | 316 tc->setMiscRegNoEffect(MISCREG_STATUS, status);
334 tc->setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus);
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| /gem5/src/arch/x86/ |
| H A D | isa.cc | 155 ISA::setMiscRegNoEffect(int miscReg, RegVal val) function in class:X86ISA::ISA
394 setMiscRegNoEffect(miscReg, newVal);
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| H A D | utility.cc | 223 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
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| /gem5/src/arch/sparc/linux/ |
| H A D | linux.hh | 200 ctc->setMiscRegNoEffect(SparcISA::MISCREG_TL, 0);
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| /gem5/src/cpu/ |
| H A D | thread_context.hh | 290 virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
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| H A D | simple_thread.hh | 553 setMiscRegNoEffect(RegIndex misc_reg, RegVal val) override
555 return isa->setMiscRegNoEffect(misc_reg, val);
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| /gem5/src/arch/mips/linux/ |
| H A D | process.cc | 167 tc->setMiscRegNoEffect(MISCREG_TP_VALUE, addr);
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| /gem5/src/arch/arm/ |
| H A D | isa.cc | 753 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
1782 setMiscRegNoEffect(MISCREG_PAR, newVal);
2049 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
2090 setMiscRegNoEffect(misc_reg, newVal);
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| H A D | utility.cc | 179 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
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| H A D | isa.hh | 445 void setMiscRegNoEffect(int misc_reg, RegVal val);
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| H A D | faults.cc | 521 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
1427 tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
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