/gem5/util/cpt_upgraders/ |
H A D | ruby-block-size-bytes.py | 3 for sec in cpt.sections(): 4 if sec == 'system.ruby': 7 cpt.set(sec, 'block_size_bytes', '64')
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H A D | x86-add-tlb.py | 4 for sec in cpt.sections(): 7 if re.search('.*sys.*\.cpu.*\.dtb$', sec): 8 cpt.set(sec, '_size', '0') 9 cpt.set(sec, 'lruSeq', '0') 11 if re.search('.*sys.*\.cpu.*\.itb$', sec): 12 cpt.set(sec, '_size', '0') 13 cpt.set(sec, 'lruSeq', '0')
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H A D | ide-dma-abort.py | 3 for sec in cpt.sections(): 5 if cpt.has_option(sec, "curSector"): 6 cpt.set(sec, "dmaAborted", "false")
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H A D | cpu-pid.py | 2 for sec in cpt.sections(): 5 if re.search('.*sys.*cpu', sec): 7 junk = cpt.get(sec, 'instCnt') 8 cpt.set(sec, '_pid', '0')
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H A D | memory-per-range.py | 5 for sec in cpt.sections(): 8 if re.search('.*sys.*\.physmem$', sec): 10 cpt.set(sec, 'nbr_of_stores', '1') 14 mem_filename = cpt.get(sec, 'filename') 15 mem_size = cpt.get(sec, '_size') 16 cpt.remove_option(sec, 'filename') 17 cpt.remove_option(sec, '_size') 20 system_name = str(sec).split('.')[0] 26 elif re.search('.*sys.*\.\w*mem$', sec): 30 raise ValueError("more than one memory detected (" + sec [all...] |
H A D | dvfs-perflevel.py | 3 for sec in cpt.sections(): 6 if re.match('^.*sys.*[._]clk_domain$', sec): 8 cpt.set(sec, '_perfLevel', ' '.join('0')) 9 elif re.match('^.*sys.*[._]voltage_domain$', sec): 11 cpt.set(sec, '_perfLevel', ' '.join('0'))
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H A D | smt-interrupts.py | 5 for sec in cpt.sections(): 8 re_cpu_match = re.match('^(.*sys.*\.cpu[^._]*)$', sec) 10 interrupts = cpt.get(sec, 'interrupts') 11 intStatus = cpt.get(sec, 'intStatus') 18 cpt.remove_option(sec, 'interrupts') 19 cpt.remove_option(sec, 'intStatus')
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H A D | arm-contextidr-el2.py | 4 for sec in cpt.sections(): 7 if re.search('.*sys.*\.cpu.*\.isa$', sec): 8 miscRegs = cpt.get(sec, 'miscRegs').split() 11 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in miscRegs))
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H A D | arm-miscreg-teehbr.py | 4 for sec in cpt.sections(): 7 if re.search('.*sys.*\.cpu.*\.isa$', sec): 8 mr = cpt.get(sec, 'miscRegs').split() 13 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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H A D | remove-arm-cpsr-mode-miscreg.py | 4 for sec in cpt.sections(): 7 if re.search('.*sys.*\.cpu.*\.isa$', sec): 8 mr = cpt.get(sec, 'miscRegs').split() 11 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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H A D | arm-gicv2-banked-regs.py | 39 for sec in cpt.sections(): 42 if not re.search('\.gic$', sec): 44 cpuEnabled = cpt.get(sec, 'cpuEnabled' ).split() 46 intEnabled = cpt.get(sec, 'intEnabled' ).split() 47 pendingInt = cpt.get(sec, 'pendingInt' ).split() 48 activeInt = cpt.get(sec, 'activeInt' ).split() 49 intPriority = cpt.get(sec, 'intPriority').split() 50 cpuTarget = cpt.get(sec, 'cpuTarget' ).split() 62 cpt.set(sec, 'intEnabled', ' '.join(intEnabled)) 63 cpt.set(sec, 'pendingIn [all...] |
H A D | isa-is-simobject.py | 25 for sec in cpt.sections(): 28 re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec) 41 for (key, value) in cpt.items(sec, raw=True): 49 cpt.remove_option(sec, key) 51 for (sec, options) in isa_sections: 55 if not cpt.has_section(sec): 56 cpt.add_section(sec) 58 if cpt.items(sec): 63 cpt.set(sec, key, value)
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H A D | arm-ccregs.py | 5 for sec in cpt.sections(): 8 re_cpu_match = re.match('^(.*sys.*\.cpu[^.]*)\.xc\.(.+)$', sec) 14 for (item,value) in cpt.items(sec): 17 intRegs = cpt.get(sec, 'intRegs').split() 25 cpt.set(sec, 'intRegs', ' '.join(intRegs)) 26 cpt.set(sec, 'ccRegs', ' '.join(ccRegs))
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H A D | arm-sve.py | 11 for sec in cpt.sections(): 14 if re.search('.*sys.*\.cpu.*\.isa$', sec): 17 cpt.set(sec, 'haveSVE', 'false') 21 cpt.set(sec, 'sveVL', '1') 24 mr = cpt.get(sec, 'miscRegs').split() 35 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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H A D | arm-gem5-gic-ext.py | 67 for sec in cpt.sections(): 68 if re.search('.*\.gic$', sec): 70 value = cpt.get(sec, reg).split(" ") 74 cpt.set(sec, reg, " ".join(value)) 77 cpt.set(sec, reg, " ".join([ default, ] * new_cpu_max))
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H A D | armv8.py | 11 for sec in cpt.sections(): 12 re_xc_match = re.match('^.*?sys.*?\.cpu(\d+)*\.xc\.*', sec) 17 fpr = cpt.get(sec, 'floatRegs.i').split() 26 cpt.set(sec, 'floatRegs.i', ' '.join(str(x) for x in fpr)) 28 ir = cpt.get(sec, 'intRegs').split() 34 cpt.set(sec, 'intRegs', ' '.join(str(x) for x in ir)) 37 for sec in cpt.sections(): 38 re_int_match = re.match("^.*?sys.*?\.cpu(\d+)*$", sec) 42 irqs = cpt.get(sec, "interrupts").split() 45 cpt.set(sec, "interrupt [all...] |
H A D | etherswitch.py | 2 for sec in cpt.sections(): 3 if sec == "system": 4 options = cpt.items(sec) 22 cpt.remove_option(sec, it[0])
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H A D | arm-hdlcd-upgrade.py | 76 for sec in cpt.sections(): 77 if re.search('.*\.hdlcd$', sec): 80 options[new] = cpt.get(sec, old) 82 cpt.remove_section(sec) 83 cpt.add_section(sec) 85 cpt.set(sec, key, value) 90 sec_dma = "%s.dmaEngine" % sec
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H A D | process-fdmap-rename.py | 13 for sec in cpt.sections(): 16 if re.match('.*\.%s.*' % fdm, sec): 17 rename = re.sub(fdm, fde, sec) 21 rename_section(cpt, sec, rename)
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H A D | arm-sysreg-mapping-ns.py | 39 for sec in cpt.sections(): 42 if re.search('.*sys.*\.cpu.*\.isa\d*$', sec): 43 mr = cpt.get(sec, 'miscRegs').split() 72 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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/gem5/src/base/ |
H A D | time.hh | 65 explicit Time(double sec) { operator=(sec); } argument 67 Time(uint64_t sec, uint64_t nsec) { set(sec, nsec); } argument 74 time_t sec() const { return _time.tv_sec; } function in class:Time 79 void sec(time_t sec) { _time.tv_sec = sec; } argument 103 void set(time_t _sec, long _nsec) { sec(_sec); nsec(_nsec); } 120 sec(othe [all...] |
H A D | time.cc | 69 return sec() * SimClock::Frequency + 76 time_t sec = this->sec(); local 81 ctime_r(&sec, buf, sizeof(buf)); 83 ctime_r(&sec, buf); 89 struct tm *tm = localtime(&sec); 127 paramOut(cp, base + ".sec", sec()); 136 paramIn(cp, base + ".sec", secs); 138 sec(sec [all...] |
/gem5/util/ |
H A D | checkpoint_aggregator.py | 67 for sec in config.sections(): 68 if re.compile("cpu").search(sec): 69 newsec = re.sub("cpu", "cpu" + str(i).zfill(num_digits), sec) 72 items = config.items(sec) 79 if re.compile("workload.FdMap256$").search(sec): 82 elif sec == "system": 84 elif sec == "Globals": 85 tick = config.getint(sec, "curTick") 90 merged_config.add_section(sec) 91 for item in config.items(sec) [all...] |
/gem5/src/base/loader/ |
H A D | object_file.cc | 76 ObjectFile::loadSection(Section *sec, const PortProxy& mem_proxy, argument 79 if (sec->size != 0) { 80 Addr addr = (sec->baseAddr & addr_mask) + offset; 81 if (sec->fileImage) { 82 mem_proxy.writeBlob(addr, sec->fileImage, sec->size); 86 mem_proxy.memsetBlob(addr, 0, sec->size);
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/gem5/src/dev/ |
H A D | mc146818.cc | 76 sec = time.tm_sec; 90 sec = bcdize(sec); 145 curTime.tm_sec = unbcdize(sec);
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