111590SCurtis.Dunham@arm.com# Copyright (c) 2016 ARM Limited 211590SCurtis.Dunham@arm.com# All rights reserved 311590SCurtis.Dunham@arm.com# 411590SCurtis.Dunham@arm.com# The license below extends only to copyright in the software and shall 511590SCurtis.Dunham@arm.com# not be construed as granting a license to any other intellectual 611590SCurtis.Dunham@arm.com# property including but not limited to intellectual property relating 711590SCurtis.Dunham@arm.com# to a hardware implementation of the functionality of the software 811590SCurtis.Dunham@arm.com# licensed hereunder. You may use the software subject to the license 911590SCurtis.Dunham@arm.com# terms below provided that you ensure that this notice is replicated 1011590SCurtis.Dunham@arm.com# unmodified and in its entirety in all distributions of the software, 1111590SCurtis.Dunham@arm.com# modified or unmodified, in source code or in binary form. 1211590SCurtis.Dunham@arm.com# 1311590SCurtis.Dunham@arm.com# Redistribution and use in source and binary forms, with or without 1411590SCurtis.Dunham@arm.com# modification, are permitted provided that the following conditions are 1511590SCurtis.Dunham@arm.com# met: redistributions of source code must retain the above copyright 1611590SCurtis.Dunham@arm.com# notice, this list of conditions and the following disclaimer; 1711590SCurtis.Dunham@arm.com# redistributions in binary form must reproduce the above copyright 1811590SCurtis.Dunham@arm.com# notice, this list of conditions and the following disclaimer in the 1911590SCurtis.Dunham@arm.com# documentation and/or other materials provided with the distribution; 2011590SCurtis.Dunham@arm.com# neither the name of the copyright holders nor the names of its 2111590SCurtis.Dunham@arm.com# contributors may be used to endorse or promote products derived from 2211590SCurtis.Dunham@arm.com# this software without specific prior written permission. 2311590SCurtis.Dunham@arm.com# 2411590SCurtis.Dunham@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2511590SCurtis.Dunham@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2611590SCurtis.Dunham@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2711590SCurtis.Dunham@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2811590SCurtis.Dunham@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2911590SCurtis.Dunham@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3011590SCurtis.Dunham@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3111590SCurtis.Dunham@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211590SCurtis.Dunham@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3311590SCurtis.Dunham@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3411590SCurtis.Dunham@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3511590SCurtis.Dunham@arm.com 3611590SCurtis.Dunham@arm.com# duplicate banked registers into new per-cpu arrays. 3711590SCurtis.Dunham@arm.comdef upgrader(cpt): 3811590SCurtis.Dunham@arm.com if cpt.get('root','isa') == 'arm': 3911590SCurtis.Dunham@arm.com for sec in cpt.sections(): 4011590SCurtis.Dunham@arm.com import re 4111590SCurtis.Dunham@arm.com 4211590SCurtis.Dunham@arm.com if not re.search('\.gic$', sec): 4311590SCurtis.Dunham@arm.com continue 4411590SCurtis.Dunham@arm.com cpuEnabled = cpt.get(sec, 'cpuEnabled' ).split() 4511590SCurtis.Dunham@arm.com 4611590SCurtis.Dunham@arm.com intEnabled = cpt.get(sec, 'intEnabled' ).split() 4711590SCurtis.Dunham@arm.com pendingInt = cpt.get(sec, 'pendingInt' ).split() 4811590SCurtis.Dunham@arm.com activeInt = cpt.get(sec, 'activeInt' ).split() 4911590SCurtis.Dunham@arm.com intPriority = cpt.get(sec, 'intPriority').split() 5011590SCurtis.Dunham@arm.com cpuTarget = cpt.get(sec, 'cpuTarget' ).split() 5111590SCurtis.Dunham@arm.com 5211590SCurtis.Dunham@arm.com b_intEnabled = intEnabled[0] 5311590SCurtis.Dunham@arm.com b_pendingInt = pendingInt[0] 5411590SCurtis.Dunham@arm.com b_activeInt = activeInt[0] 5511590SCurtis.Dunham@arm.com 5611590SCurtis.Dunham@arm.com del intEnabled[0] 5711590SCurtis.Dunham@arm.com del pendingInt[0] 5811590SCurtis.Dunham@arm.com del activeInt[0] 5911590SCurtis.Dunham@arm.com del intPriority[0:32] # unused; overlapped with bankedIntPriority 6011590SCurtis.Dunham@arm.com del cpuTarget[0:32] 6111590SCurtis.Dunham@arm.com 6211590SCurtis.Dunham@arm.com cpt.set(sec, 'intEnabled', ' '.join(intEnabled)) 6311590SCurtis.Dunham@arm.com cpt.set(sec, 'pendingInt', ' '.join(pendingInt)) 6411590SCurtis.Dunham@arm.com cpt.set(sec, 'activeInt', ' '.join(activeInt)) 6511590SCurtis.Dunham@arm.com cpt.set(sec, 'intPriority',' '.join(intPriority)) 6611590SCurtis.Dunham@arm.com cpt.set(sec, 'cpuTarget', ' '.join(cpuTarget)) 6711590SCurtis.Dunham@arm.com 6811590SCurtis.Dunham@arm.com b_intPriority = cpt.get(sec, '*bankedIntPriority').split() 6911590SCurtis.Dunham@arm.com cpt.remove_option(sec, '*bankedIntPriority') 7011590SCurtis.Dunham@arm.com 7111590SCurtis.Dunham@arm.com for cpu in xrange(0, 255): 7211590SCurtis.Dunham@arm.com if cpuEnabled[cpu] == 'true': 7311590SCurtis.Dunham@arm.com intPriority = b_intPriority[cpu*32 : (cpu+1)*32] 7411590SCurtis.Dunham@arm.com new_sec = "%s.bankedRegs%u" % (sec, cpu) 7511590SCurtis.Dunham@arm.com cpt.add_section(new_sec) 7611590SCurtis.Dunham@arm.com cpt.set(new_sec, 'intEnabled', b_intEnabled) 7711590SCurtis.Dunham@arm.com cpt.set(new_sec, 'pendingInt', b_pendingInt) 7811590SCurtis.Dunham@arm.com cpt.set(new_sec, 'activeInt', b_activeInt) 7911590SCurtis.Dunham@arm.com cpt.set(new_sec, 'intPriority',' '.join(intPriority)) 80