1# Copyright (c) 2016 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 36# duplicate banked registers into new per-cpu arrays. 37def upgrader(cpt): 38 if cpt.get('root','isa') == 'arm': 39 for sec in cpt.sections(): 40 import re 41 42 if not re.search('\.gic$', sec): 43 continue 44 cpuEnabled = cpt.get(sec, 'cpuEnabled' ).split() 45 46 intEnabled = cpt.get(sec, 'intEnabled' ).split() 47 pendingInt = cpt.get(sec, 'pendingInt' ).split() 48 activeInt = cpt.get(sec, 'activeInt' ).split() 49 intPriority = cpt.get(sec, 'intPriority').split() 50 cpuTarget = cpt.get(sec, 'cpuTarget' ).split() 51 52 b_intEnabled = intEnabled[0] 53 b_pendingInt = pendingInt[0] 54 b_activeInt = activeInt[0] 55 56 del intEnabled[0] 57 del pendingInt[0] 58 del activeInt[0] 59 del intPriority[0:32] # unused; overlapped with bankedIntPriority 60 del cpuTarget[0:32] 61 62 cpt.set(sec, 'intEnabled', ' '.join(intEnabled)) 63 cpt.set(sec, 'pendingInt', ' '.join(pendingInt)) 64 cpt.set(sec, 'activeInt', ' '.join(activeInt)) 65 cpt.set(sec, 'intPriority',' '.join(intPriority)) 66 cpt.set(sec, 'cpuTarget', ' '.join(cpuTarget)) 67 68 b_intPriority = cpt.get(sec, '*bankedIntPriority').split() 69 cpt.remove_option(sec, '*bankedIntPriority') 70 71 for cpu in xrange(0, 255): 72 if cpuEnabled[cpu] == 'true': 73 intPriority = b_intPriority[cpu*32 : (cpu+1)*32] 74 new_sec = "%s.bankedRegs%u" % (sec, cpu) 75 cpt.add_section(new_sec) 76 cpt.set(new_sec, 'intEnabled', b_intEnabled) 77 cpt.set(new_sec, 'pendingInt', b_pendingInt) 78 cpt.set(new_sec, 'activeInt', b_activeInt) 79 cpt.set(new_sec, 'intPriority',' '.join(intPriority)) 80