Searched refs:readMiscReg (Results 26 - 50 of 66) sorted by relevance

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/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc633 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
671 HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2);
677 HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3);
739 HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR);
766 HCPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3);
780 SCTLR sctlr = ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1));
781 HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
782 SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
994 CPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2);
1000 CPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL
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/gem5/src/arch/arm/
H A Dprocess.cc111 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
117 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
130 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
133 CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
141 FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
213 const AA64PFR0 pf_r0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
222 const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
239 const AA64ISAR1 isa_r1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
247 const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
H A Dtlb.cc1025 AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
1304 cpsr = tc->readMiscReg(MISCREG_CPSR);
1321 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1322 ttbcr = tc->readMiscReg(MISCREG_TCR_EL1);
1324 tc->readMiscReg(MISCREG_TTBR1_EL1) :
1325 tc->readMiscReg(MISCREG_TTBR0_EL1);
1331 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL2);
1332 ttbcr = tc->readMiscReg(MISCREG_TCR_EL2);
1336 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL3);
1337 ttbcr = tc->readMiscReg(MISCREG_TCR_EL
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H A Dtable_walker.cc241 TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType);
269 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
270 currState->vtcr = currState->tc->readMiscReg(MISCREG_VTCR_EL2);
274 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
275 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1);
279 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2);
280 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2);
284 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3);
285 currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL3);
291 currState->hcr = currState->tc->readMiscReg(MISCREG_HCR_EL
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H A Dutility.hh149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
348 return tc->readMiscReg(MISCREG_CONTEXTIDR);
H A Disa.hh424 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
429 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
444 RegVal readMiscReg(int misc_reg, ThreadContext *tc);
/gem5/src/arch/x86/
H A Dfaults.cc194 CR0 cr0 = tc->readMiscReg(MISCREG_CR0);
252 PCState pc(0x000000000000fff0ULL + tc->readMiscReg(MISCREG_CS_BASE));
307 HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
319 tc->pcState(tc->readMiscReg(MISCREG_CS_BASE));
/gem5/src/arch/alpha/
H A Disa.cc98 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
/gem5/src/arch/mips/
H A Disa.hh94 RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
H A Dmt.hh73 return otc->readMiscReg(reg.index());
199 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
200 TCStatusReg tcStatus = tc->readMiscReg(MISCREG_TC_STATUS);
279 VPEControlReg vpeControl = tc->readMiscReg(MISCREG_VPE_CONTROL);
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc142 const uint64_t value(tc->readMiscReg(ri.idx));
221 CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
234 const uint64_t value(tc->readMiscReg(ri.idx));
268 value = tc->readMiscReg(ri.idx);
270 value = tc->readMiscReg(ri.idx);
/gem5/src/arch/sparc/
H A Dtlb.cc875 pkt->setBE(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
880 pkt->setBE(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
883 pkt->setBE(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
890 pkt->setBE(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
946 pkt->setBE(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
980 pkt->setBE(tc->readMiscReg(MISCREG_MMU_PART_ID));
1167 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1182 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1192 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1195 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEX
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H A Disa.hh187 RegVal readMiscReg(int miscReg, ThreadContext *tc);
/gem5/src/cpu/o3/
H A Ddyn_inst.hh140 readMiscReg(int misc_reg) override
142 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
178 return this->cpu->readMiscReg(reg.index(), this->threadNumber);
H A Dthread_context.hh393 readMiscReg(RegIndex misc_reg) override
395 return cpu->readMiscReg(misc_reg, thread->threadId());
/gem5/src/arch/riscv/
H A Dinterrupts.hh78 STATUS status = tc->readMiscReg(MISCREG_STATUS);
H A Disa.cc112 ISA::readMiscReg(int misc_reg, ThreadContext *tc) function in class:RiscvISA::ISA
/gem5/src/dev/arm/
H A Dgeneric_timer.hh227 RegVal readMiscReg(int misc_reg, unsigned cpu);
290 RegVal readMiscReg(int misc_reg) override;
H A Dgic_v3_cpu_interface.cc114 Gicv3CPUInterface::readMiscReg(int misc_reg) function in class:Gicv3CPUInterface
171 return readMiscReg(MISCREG_ICV_IGRPEN0_EL1);
188 return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
221 return readMiscReg(MISCREG_ICV_RPR_EL1);
256 return readMiscReg(MISCREG_ICV_HPPIR0_EL1);
286 return readMiscReg(MISCREG_ICV_HPPIR1_EL1);
316 return readMiscReg(MISCREG_ICV_BPR0_EL1);
359 return readMiscReg(MISCREG_ICV_PMR_EL1);
392 return readMiscReg(MISCREG_ICV_IAR0_EL1);
448 return readMiscReg(MISCREG_ICV_IAR1_EL
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H A Dgeneric_timer.cc421 GenericTimer::readMiscReg(int reg, unsigned cpu) function in class:GenericTimer
518 GenericTimerISA::readMiscReg(int reg) function in class:GenericTimerISA
520 RegVal value = parent.readMiscReg(reg, cpu);
/gem5/src/cpu/minor/
H A Dexec_context.hh362 readMiscReg(int misc_reg) override
364 return thread.readMiscReg(misc_reg);
378 return thread.readMiscReg(reg.index());
/gem5/src/cpu/simple/
H A Dexec_context.hh391 return thread->readMiscReg(reg.index());
408 readMiscReg(int misc_reg) override
411 return thread->readMiscReg(misc_reg);
/gem5/src/cpu/
H A Dexec_context.hh208 virtual RegVal readMiscReg(int misc_reg) = 0;
/gem5/src/cpu/kvm/
H A Dx86_cpu.cc696 regs.rip = tc->instAddr() - tc->readMiscReg(MISCREG_CS_BASE);
806 RFLAGS rflags_nocc(tc->readMiscReg(MISCREG_RFLAGS));
830 fpu.fsw = tc->readMiscReg(MISCREG_FSW);
927 e.data = tc->readMiscReg(msrMap.at(*it));
1262 kvm_run.apic_base = tc->readMiscReg(MISCREG_APIC_BASE);
1263 kvm_run.cr8 = tc->readMiscReg(MISCREG_CR8);
1268 kvm_run.cr8 = tc->readMiscReg(MISCREG_CR8);
/gem5/src/cpu/checker/
H A Dcpu.hh461 readMiscReg(int misc_reg) override
463 return thread->readMiscReg(misc_reg);
489 return thread->readMiscReg(reg.index());

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