Searched refs:override (Results 276 - 300 of 403) sorted by relevance

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/gem5/src/mem/
H A Dphysical.hh244 void serialize(CheckpointOut &cp) const override; member in class:PhysicalMemory
261 void unserialize(CheckpointIn &cp) override; member in class:PhysicalMemory
/gem5/src/arch/alpha/
H A Disa.hh95 void serialize(CheckpointOut &cp) const override; member in class:AlphaISA::ISA
96 void unserialize(CheckpointIn &cp) override; member in class:AlphaISA::ISA
/gem5/src/arch/x86/
H A Disa.hh137 void serialize(CheckpointOut &cp) const override; member in class:X86ISA::ISA
138 void unserialize(CheckpointIn &cp) override; member in class:X86ISA::ISA
/gem5/src/mem/cache/prefetch/
H A Dbop.hh146 void notifyFill(const PacketPtr& pkt) override; member in class:BOPPrefetcher
154 std::vector<AddrPriority> &addresses) override; member in class:BOPPrefetcher
H A Dsbooe.hh149 void notifyFill(const PacketPtr& pkt) override; member in class:SBOOEPrefetcher
155 std::vector<AddrPriority> &addresses) override; member in class:SBOOEPrefetcher
H A Dbase.hh77 void notify(const PacketPtr &pkt) override; member in class:BasePrefetcher::PrefetchListener
358 void regStats() override; member in class:BasePrefetcher
363 void regProbeListeners() override; member in class:BasePrefetcher
/gem5/src/python/
H A Dimporter.py71 override = os.environ.get('M5_OVERRIDE_PY_SOURCE', 'false').lower()
72 if override in ('true', 'yes') and os.path.exists(abspath):
/gem5/src/cpu/testers/memtest/
H A Dmemtest.hh79 void regStats() override; member in class:MemTest
82 PortID idx=InvalidPortID) override; member in class:MemTest
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.hh72 PortID idx=InvalidPortID) override; member in class:RubyDirectedTester
76 void init() override; member in class:RubyDirectedTester
/gem5/src/cpu/testers/garnet_synthetic_traffic/
H A DGarnetSyntheticTraffic.hh62 void init() override; member in class:GarnetSyntheticTraffic
68 PortID idx=InvalidPortID) override; member in class:GarnetSyntheticTraffic
/gem5/src/arch/generic/
H A Dtypes.hh118 serialize(CheckpointOut &cp) const override
125 unserialize(CheckpointIn &cp) override
267 serialize(CheckpointOut &cp) const override
275 unserialize(CheckpointIn &cp) override
348 serialize(CheckpointOut &cp) const override
355 unserialize(CheckpointIn &cp) override
445 serialize(CheckpointOut &cp) const override
453 unserialize(CheckpointIn &cp) override
/gem5/src/cpu/pred/
H A Dmultiperspective_perceptron.hh491 override
526 void setBitRequirements() const override
542 override
568 void setBitRequirements() const override
590 override
605 void setBitRequirements() const override
619 override
634 override
659 void setBitRequirements() const override
676 override
1024 void init() override; member in class:MultiperspectivePerceptron
1026 void uncondBranch(ThreadID tid, Addr pc, void * &bp_history) override; member in class:MultiperspectivePerceptron
1027 void squash(ThreadID tid, void *bp_history) override; member in class:MultiperspectivePerceptron
1028 bool lookup(ThreadID tid, Addr instPC, void * &bp_history) override; member in class:MultiperspectivePerceptron
1032 Addr corrTarget = MaxAddr) override; member in class:MultiperspectivePerceptron
1033 void btbUpdate(ThreadID tid, Addr branch_addr, void* &bp_history) override; member in class:MultiperspectivePerceptron
[all...]
/gem5/src/dev/arm/
H A Dsmmu_v3_slaveifc.hh120 Port& getPort(const std::string &name, PortID id) override; member in class:SMMUv3SlaveInterface
137 DrainState drain() override; member in class:SMMUv3SlaveInterface
H A Dvgic.hh184 void serialize(CheckpointOut &cp) const override; member in struct:VGic::vcpuIntData
185 void unserialize(CheckpointIn &cp) override; member in struct:VGic::vcpuIntData
200 AddrRangeList getAddrRanges() const override; member in class:VGic
202 Tick read(PacketPtr pkt) override; member in class:VGic
203 Tick write(PacketPtr pkt) override; member in class:VGic
205 void serialize(CheckpointOut &cp) const override; member in class:VGic
206 void unserialize(CheckpointIn &cp) override; member in class:VGic
/gem5/src/sim/
H A Dprocess.hh69 void serialize(CheckpointOut &cp) const override; member in class:Process
70 void unserialize(CheckpointIn &cp) override; member in class:Process
72 void initState() override; member in class:Process
73 DrainState drain() override; member in class:Process
111 // override of virtual SimObject method: register statistics
112 void regStats() override; member in class:Process
140 * instead, so they can override this method to return false.
/gem5/src/cpu/testers/traffic_gen/
H A Dbase.hh249 PortID idx=InvalidPortID) override; member in class:BaseTrafficGen
251 void init() override; member in class:BaseTrafficGen
253 DrainState drain() override; member in class:BaseTrafficGen
255 void serialize(CheckpointOut &cp) const override; member in class:BaseTrafficGen
256 void unserialize(CheckpointIn &cp) override; member in class:BaseTrafficGen
/gem5/src/dev/net/
H A Dns_gige.hh341 PortID idx=InvalidPortID) override; member in class:NSGigE
343 Tick writeConfig(PacketPtr pkt) override; member in class:NSGigE
345 Tick read(PacketPtr pkt) override; member in class:NSGigE
346 Tick write(PacketPtr pkt) override; member in class:NSGigE
354 void serialize(CheckpointOut &cp) const override; member in class:NSGigE
355 void unserialize(CheckpointIn &cp) override; member in class:NSGigE
357 void drainResume() override; member in class:NSGigE
H A Detherswitch.hh65 PortID idx=InvalidPortID) override; member in class:EtherSwitch
192 void serialize(CheckpointOut &cp) const override; member in class:EtherSwitch
193 void unserialize(CheckpointIn &cp) override; member in class:EtherSwitch
/gem5/src/cpu/
H A Dbase.hh204 PortID idx=InvalidPortID) override;
316 void init() override;
317 void startup() override;
318 void regStats() override;
320 void regProbePoints() override;
417 void serialize(CheckpointOut &cp) const override;
429 void unserialize(CheckpointIn &cp) override;
/gem5/src/python/pybind11/
H A Devent.cc63 * C++ cousin, PyEvents need to override __call__ instead of
76 void process() override {
83 void acquireImpl() override {
93 void releaseImpl() override {
/gem5/src/mem/ruby/system/
H A DRubyPort.hh149 void init() override; member in class:RubyPort
152 PortID idx=InvalidPortID) override; member in class:RubyPort
165 DrainState drain() override; member in class:RubyPort
/gem5/src/systemc/utils/
H A Dvcd.cc331 output(std::ostream &os) override
349 std::string vcdType() override { return "real"; }
352 output(std::ostream &os) override
375 output(std::ostream &os) override
398 finalize() override
405 output(std::ostream &os) override
450 finalize() override
457 output(std::ostream &os) override
480 std::string vcdType() override { return "real"; }
483 output(std::ostream &os) override
[all...]
/gem5/ext/nomali/lib/
H A Djobslot.hh49 void writeReg(RegAddr idx, uint32_t value) override; member in class:NoMali::JobSlot
H A Daddrspace.hh49 void writeReg(RegAddr idx, uint32_t value) override; member in class:NoMali::AddrSpace
/gem5/src/cpu/minor/
H A Dpipeline.hh127 void evaluate() override; member in class:Minor::Pipeline

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