/gem5/src/dev/arm/ |
H A D | gic_v3_cpu_interface.hh | 301 void generateSGI(RegVal val, Gicv3::GroupId group); 339 RegVal bpr1(Gicv3::GroupId group); 341 RegVal readBankedMiscReg(MiscRegIndex misc_reg) const; 342 void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const; 350 RegVal readMiscReg(int misc_reg) override; 351 void setMiscReg(int misc_reg, RegVal val) override;
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H A D | generic_timer.hh | 226 void setMiscReg(int misc_reg, unsigned cpu, RegVal val); 227 RegVal readMiscReg(int misc_reg, unsigned cpu); 289 void setMiscReg(int misc_reg, RegVal val) override; 290 RegVal readMiscReg(int misc_reg) override;
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H A D | gic_v3_cpu_interface.cc | 113 RegVal 116 RegVal value = isa->readMiscRegNoEffect(misc_reg); 734 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val) 1292 RegVal old_icc_pmr_el1 = 1491 RegVal old_val = isa->readMiscRegNoEffect(misc_reg); 1616 RegVal 1624 Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const 1727 RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg); 1743 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i); 1744 RegVal vapr [all...] |
H A D | generic_timer.cc | 315 GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val) 420 RegVal 511 GenericTimerISA::setMiscReg(int reg, RegVal val) 517 RegVal 520 RegVal value = parent.readMiscReg(reg, cpu);
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/gem5/src/arch/mips/ |
H A D | interrupts.cc | 148 RegVal compare = tc->readMiscRegNoEffect(MISCREG_COMPARE); 149 RegVal count = tc->readMiscRegNoEffect(MISCREG_COUNT);
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H A D | mt.hh | 55 static inline RegVal 80 setRegOtherThread(ThreadContext *tc, const RegId& reg, RegVal val, 103 static inline RegVal 111 setRegOtherThread(ExecContext *xc, const RegId& reg, RegVal val,
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H A D | process.cc | 201 RegVal 209 MipsProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
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/gem5/src/arch/x86/ |
H A D | process.cc | 122 Process *p, RegVal flags) 453 RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32); 455 RegVal lstar = (RegVal)syscallCodeVirtAddr; 457 RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF 1070 RegVal 1078 X86_64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val) 1086 Process *p, RegVal flag [all...] |
H A D | tlb.cc | 188 //The index is multiplied by the size of a RegVal so that 191 req->setPaddr((Addr)regNum * sizeof(RegVal)); 203 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal));
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/gem5/src/arch/sparc/ |
H A D | faults.hh | 357 void getREDVector(RegVal TT, Addr &PC, Addr &NPC); 359 void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT); 361 void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, 362 RegVal TL);
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H A D | isa.cc | 176 RegVal 251 return (RegVal)pstate; 274 return (RegVal)hpstate; 337 RegVal 386 ISA::setMiscRegNoEffect(int miscReg, RegVal val) 567 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) 569 RegVal new_val = val;
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H A D | ua2005.cc | 92 ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) 246 RegVal
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/gem5/src/cpu/o3/ |
H A D | cpu.cc | 1168 RegVal 1175 RegVal 1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) 1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) 1198 RegVal 1206 RegVal 1258 RegVal 1267 FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) 1275 FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val) 1308 FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal va [all...] |
/gem5/src/arch/riscv/ |
H A D | process.cc | 254 RegVal 259 RegVal retval = 0; 267 RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
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/gem5/src/arch/alpha/ |
H A D | process.cc | 224 RegVal 232 AlphaProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val) 250 tc->setIntReg(SyscallSuccessReg, (RegVal)-1);
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/gem5/src/arch/arm/ |
H A D | process.cc | 482 RegVal 489 RegVal 496 RegVal 515 RegVal 523 ArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val) 530 ArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val)
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H A D | pmu.cc | 57 const RegVal PMU::reg_pmcr_wr_mask = 0x39; 194 PMU::setMiscReg(int misc_reg, RegVal val) 302 RegVal 305 RegVal val(readMiscRegInt(misc_reg)); 311 RegVal 654 PMU::setOverflowStatus(RegVal new_val)
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H A D | isa.cc | 427 RegVal 451 RegVal 506 RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 688 RegVal val = readMiscRegNoEffect(misc_reg); 697 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 753 ISA::setMiscRegNoEffect(int misc_reg, RegVal val) 775 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 778 RegVal newVal = val; 850 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 1069 miscRegs[sctlr_idx] = (RegVal)new_sctl [all...] |
H A D | utility.hh | 267 RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc); 270 RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
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H A D | isa.hh | 377 RegVal miscRegs[NumMiscRegs]; 443 RegVal readMiscRegNoEffect(int misc_reg) const; 444 RegVal readMiscReg(int misc_reg, ThreadContext *tc); 445 void setMiscRegNoEffect(int misc_reg, RegVal val); 446 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
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/gem5/src/arch/power/ |
H A D | process.cc | 276 RegVal 284 PowerProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
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/gem5/src/base/ |
H A D | types.hh | 168 typedef uint64_t RegVal; typedef
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/gem5/src/cpu/ |
H A D | base_dyn_inst.hh | 671 void setIntRegOperand(const StaticInst *si, int idx, RegVal val) 677 void setCCRegOperand(const StaticInst *si, int idx, RegVal val) 691 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
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/gem5/src/arch/power/linux/ |
H A D | process.cc | 471 RegVal 481 PowerLinuxProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
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/gem5/src/sim/ |
H A D | process.cc | 145 Process *np, RegVal flags) 404 RegVal
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