Searched refs:RegVal (Results 51 - 75 of 83) sorted by relevance

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/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.hh301 void generateSGI(RegVal val, Gicv3::GroupId group);
339 RegVal bpr1(Gicv3::GroupId group);
341 RegVal readBankedMiscReg(MiscRegIndex misc_reg) const;
342 void setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const;
350 RegVal readMiscReg(int misc_reg) override;
351 void setMiscReg(int misc_reg, RegVal val) override;
H A Dgeneric_timer.hh226 void setMiscReg(int misc_reg, unsigned cpu, RegVal val);
227 RegVal readMiscReg(int misc_reg, unsigned cpu);
289 void setMiscReg(int misc_reg, RegVal val) override;
290 RegVal readMiscReg(int misc_reg) override;
H A Dgic_v3_cpu_interface.cc113 RegVal
116 RegVal value = isa->readMiscRegNoEffect(misc_reg);
734 Gicv3CPUInterface::setMiscReg(int misc_reg, RegVal val)
1292 RegVal old_icc_pmr_el1 =
1491 RegVal old_val = isa->readMiscRegNoEffect(misc_reg);
1616 RegVal
1624 Gicv3CPUInterface::setBankedMiscReg(MiscRegIndex misc_reg, RegVal val) const
1727 RegVal apr = isa->readMiscRegNoEffect(apr_misc_reg);
1743 RegVal vapr0 = isa->readMiscRegNoEffect(MISCREG_ICH_AP0R0_EL2 + i);
1744 RegVal vapr
[all...]
H A Dgeneric_timer.cc315 GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val)
420 RegVal
511 GenericTimerISA::setMiscReg(int reg, RegVal val)
517 RegVal
520 RegVal value = parent.readMiscReg(reg, cpu);
/gem5/src/arch/mips/
H A Dinterrupts.cc148 RegVal compare = tc->readMiscRegNoEffect(MISCREG_COMPARE);
149 RegVal count = tc->readMiscRegNoEffect(MISCREG_COUNT);
H A Dmt.hh55 static inline RegVal
80 setRegOtherThread(ThreadContext *tc, const RegId& reg, RegVal val,
103 static inline RegVal
111 setRegOtherThread(ExecContext *xc, const RegId& reg, RegVal val,
H A Dprocess.cc201 RegVal
209 MipsProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
/gem5/src/arch/x86/
H A Dprocess.cc122 Process *p, RegVal flags)
453 RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
455 RegVal lstar = (RegVal)syscallCodeVirtAddr;
457 RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
1070 RegVal
1078 X86_64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
1086 Process *p, RegVal flag
[all...]
H A Dtlb.cc188 //The index is multiplied by the size of a RegVal so that
191 req->setPaddr((Addr)regNum * sizeof(RegVal));
203 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(RegVal));
/gem5/src/arch/sparc/
H A Dfaults.hh357 void getREDVector(RegVal TT, Addr &PC, Addr &NPC);
359 void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT);
361 void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT,
362 RegVal TL);
H A Disa.cc176 RegVal
251 return (RegVal)pstate;
274 return (RegVal)hpstate;
337 RegVal
386 ISA::setMiscRegNoEffect(int miscReg, RegVal val)
567 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
569 RegVal new_val = val;
H A Dua2005.cc92 ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
246 RegVal
/gem5/src/cpu/o3/
H A Dcpu.cc1168 RegVal
1175 RegVal
1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid)
1198 RegVal
1206 RegVal
1258 RegVal
1267 FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val)
1275 FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val)
1308 FullO3CPU<Impl>::setCCReg(PhysRegIdPtr phys_reg, RegVal va
[all...]
/gem5/src/arch/riscv/
H A Dprocess.cc254 RegVal
259 RegVal retval = 0;
267 RiscvProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
/gem5/src/arch/alpha/
H A Dprocess.cc224 RegVal
232 AlphaProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
250 tc->setIntReg(SyscallSuccessReg, (RegVal)-1);
/gem5/src/arch/arm/
H A Dprocess.cc482 RegVal
489 RegVal
496 RegVal
515 RegVal
523 ArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val)
530 ArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val)
H A Dpmu.cc57 const RegVal PMU::reg_pmcr_wr_mask = 0x39;
194 PMU::setMiscReg(int misc_reg, RegVal val)
302 RegVal
305 RegVal val(readMiscRegInt(misc_reg));
311 RegVal
654 PMU::setOverflowStatus(RegVal new_val)
H A Disa.cc427 RegVal
451 RegVal
506 RegVal val = readMiscRegNoEffect(MISCREG_CPACR);
688 RegVal val = readMiscRegNoEffect(misc_reg);
697 RegVal mask = readMiscRegNoEffect(MISCREG_NSACR);
753 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
775 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
778 RegVal newVal = val;
850 RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR);
1069 miscRegs[sctlr_idx] = (RegVal)new_sctl
[all...]
H A Dutility.hh267 RegVal readMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
270 RegVal getMPIDR(ArmSystem *arm_sys, ThreadContext *tc);
H A Disa.hh377 RegVal miscRegs[NumMiscRegs];
443 RegVal readMiscRegNoEffect(int misc_reg) const;
444 RegVal readMiscReg(int misc_reg, ThreadContext *tc);
445 void setMiscRegNoEffect(int misc_reg, RegVal val);
446 void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc);
/gem5/src/arch/power/
H A Dprocess.cc276 RegVal
284 PowerProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
/gem5/src/base/
H A Dtypes.hh168 typedef uint64_t RegVal; typedef
/gem5/src/cpu/
H A Dbase_dyn_inst.hh671 void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
677 void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
691 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
/gem5/src/arch/power/linux/
H A Dprocess.cc471 RegVal
481 PowerLinuxProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
/gem5/src/sim/
H A Dprocess.cc145 Process *np, RegVal flags)
404 RegVal

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