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/gem5/src/arch/x86/isa/formats/
H A Dcpuid.isa5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
/gem5/src/base/
H A Dintmath.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
H A Dsocket.ccdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
H A Dcprintf.ccdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
H A Dcirclebuf.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
H A Dstr.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/base/loader/
H A Dsymtab.ccdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/sim/
H A Dinit_signals.ccdiff 11080:31ab5ca6836d Fri Sep 04 13:13:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> sim: Fix time unit in abort message
/gem5/src/arch/sparc/
H A Dmmapped_ipr.hhdiff 8748:01be402c5bf1 Mon Oct 10 03:31:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
/gem5/src/arch/alpha/
H A Disa_traits.hhdiff 3457:7479ebe49444 Tue Oct 31 16:02:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR.
diff 3454:26850ac19a39 Tue Oct 31 03:37:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.
diff 3093:b09c33e66bce Thu Aug 31 20:51:00 EDT 2006 Korey Sewell <ksewell@umich.edu> add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models

src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA
diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Dinterrupts_and_exceptions.pydiff 5812:d12ff89c7692 Sun Jan 25 23:31:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a bug in the iret microcode.
/gem5/src/arch/x86/regs/
H A Dmisc.hhdiff 11324:31ca646c7685 Sat Feb 06 20:21:00 EST 2016 Steve Reinhardt <steve.reinhardt@amd.com> x86: create function to check miscreg validity

In the process of trying to get rid of an '== false' comparison,
it became apparent that a slightly more involved solution was
needed. Split this out into its own changeset since it's not
a totally trivial local change like the others.
/gem5/src/systemc/core/
H A Dsc_export.ccdiff 13048:9ae0bf1b32e6 Wed Aug 08 22:31:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement sc_export.

This change ignores the rule that sc_exports all have to be bound
exactly once and only by the end of elaboration. If it's bound more
than once, then the earlier binding will be overwritten, and if it's
not bound at all then it will act like a null pointer. To accomodate
doing those checks in the future, the sc_export_base constructor and
destructor are in the .cc file even though they do very little so that
they can be extended to track a list of all exports which exist.

Change-Id: Ie9a3416b8fa87bca55bc9f87f3238c4de3c2e729
Reviewed-on: https://gem5-review.googlesource.com/12079
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
H A Dsc_module_name.ccdiff 12863:ed8c2541cb30 Thu May 31 21:42:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Construct and manage a module name stack.

Change-Id: I5f7f64d6c3d7e08ec6d2529f3c5d84fbfc2c421b
Reviewed-on: https://gem5-review.googlesource.com/10850
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/ext/core/
H A Dsc_export.hhdiff 13048:9ae0bf1b32e6 Wed Aug 08 22:31:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement sc_export.

This change ignores the rule that sc_exports all have to be bound
exactly once and only by the end of elaboration. If it's bound more
than once, then the earlier binding will be overwritten, and if it's
not bound at all then it will act like a null pointer. To accomodate
doing those checks in the future, the sc_export_base constructor and
destructor are in the .cc file even though they do very little so that
they can be extended to track a list of all exports which exist.

Change-Id: Ie9a3416b8fa87bca55bc9f87f3238c4de3c2e729
Reviewed-on: https://gem5-review.googlesource.com/12079
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/alpha/isa/
H A Dint.isadiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/gpu-compute/
H A Dwavefront.hhdiff 11643:42a1873be45c Fri Sep 16 00:31:00 EDT 2016 Alexandru Dutu <alexandru.dutu@amd.com> gpu-compute: Refactoring Wavefront::dynWaveId
/gem5/configs/example/
H A Detrace_replay.pydiff 12430:11cb907bd81b Wed Jan 03 17:31:00 EST 2018 Chen Zou <chenzou@uchicago.edu> configs: Fill in the cpu.isa field in etrace_replay.py since no default are provided now

Change-Id: I5f337b9969820bd74ed67e576e2d1a8e4666ecdb
Reviewed-on: https://gem5-review.googlesource.com/7021
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/arm/insts/
H A Dpseudo.hh10611:3bba9f2d0c7d Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Raise an alignment fault if a PC has illegal alignment

We currently don't handle unaligned PCs correctly. There is one check
for unaligned PCs in the TLB when running in aarch64 mode, but this
check does not cover cases where the CPU does not do a TLB lookup when
decoding an instruction (e.g., a branch stays within the same cache
line). Additionally, the Decoder class sometimes throws an assertion
for unaligned PCs which breaks speculation.

This changeset introduces a decoder fault bit field in the ExtMachInst
structure. This field can be used to signal a decoder failure. If set,
the decoder generates an internal gem5fault instruction instead of a
normal instruction. This instruction in turns either panics (fault
type PANIC), returns an PCAlignmentFault (fault type UNALIGNED,
aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32).

The patch causes minor changes to the realview64 regressions, and a
stats bump will follow.
/gem5/src/arch/mips/
H A Dinterrupts.ccdiff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
/gem5/src/arch/x86/
H A DX86System.pydiff 5627:31eac202dbd1 Sat Oct 11 02:43:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create SimObjects in python and C++ to represent the ACPI system description tables.
/gem5/src/cpu/
H A DCheckerCPU.pydiff 8733:64a7bf8fa56c Tue Jan 31 10:46:00 EST 2012 Geoffrey Blake <geoffrey.blake@arm.com> CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.
/gem5/src/cpu/o3/
H A DO3Checker.pydiff 8733:64a7bf8fa56c Tue Jan 31 10:46:00 EST 2012 Geoffrey Blake <geoffrey.blake@arm.com> CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.
/gem5/src/cpu/simple/
H A DBaseSimpleCPU.pydiff 8733:64a7bf8fa56c Tue Jan 31 10:46:00 EST 2012 Geoffrey Blake <geoffrey.blake@arm.com> CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.
/gem5/src/dev/pci/
H A DPciHost.pydiff 12474:31aaa43d1401 Fri Jan 22 10:40:00 EST 2016 Glenn Bergmans <glenn.bergmans@arm.com> arm: DT autogeneration - generate PCI node

Enables automatic generation of Device Trees for RealView PCI host
controllers. Note that some parts are more hard coded than you'd want,
but this is due to the limited understanding the PCI host has of its
configuration (i.e. it doesn't know all memory ranges). Fixing this,
for now at least, went beyond the scope and intentions of the
Device Tree generating code: use with care!

Change-Id: I2041871e0eb4d04fb5191257c47dd38649d1c0cc
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5967
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

Completed in 98 milliseconds

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