1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_MMAPPED_IPR_HH__
32#define __ARCH_SPARC_MMAPPED_IPR_HH__
33
34/**
35 * @file
36 *
37 * ISA-specific helper functions for memory mapped IPR accesses.
38 */
39
40#include "arch/generic/mmapped_ipr.hh"
41#include "arch/sparc/tlb.hh"
42#include "cpu/thread_context.hh"
43#include "mem/packet.hh"
44
45namespace SparcISA
46{
47
48inline Cycles
49handleIprRead(ThreadContext *xc, Packet *pkt)
50{
51    if (GenericISA::isGenericIprAccess(pkt))
52        return GenericISA::handleGenericIprRead(xc, pkt);
53    else
54        return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegRead(xc, pkt);
55}
56
57inline Cycles
58handleIprWrite(ThreadContext *xc, Packet *pkt)
59{
60    if (GenericISA::isGenericIprAccess(pkt))
61        return GenericISA::handleGenericIprWrite(xc, pkt);
62    else
63        return dynamic_cast<TLB *>(xc->getDTBPtr())->doMmuRegWrite(xc, pkt);
64}
65
66
67} // namespace SparcISA
68
69#endif
70