Searched hist:2010 (Results 601 - 625 of 929) sorted by relevance

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/gem5/src/arch/mips/
H A Dlocked_mem.hhdiff 7783:9b880b40ac10 Tue Dec 07 19:19:00 EST 2010 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Make all instructions that write a misc. register not perform the write until commit.

ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.

Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes. Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
diff 7676:92274350b953 Fri Sep 10 17:58:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: fix sorting of includes and whitespace in some files
H A Dtlb.hhdiff 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
diff 7461:5a07045d0af2 Tue Jun 15 04:18:00 EDT 2010 Nathan Binkert <nate@binkert.org> stats: only consider a formula initialized if there is a formula
/gem5/configs/splash2/
H A Drun.pydiff 7716:fa706473bcd5 Fri Oct 22 23:59:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Configs: Stop setting the "mem" parameter in splash2 config files.

This parameter is no longer used, and trying to set it like these scripts were
gives a simobject two parents and causes the simulation to die.
diff 7525:722f2ad014a7 Tue Aug 17 08:06:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once. The C++ Root object already panics if more than one is
created. This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists). It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone. Users who use
configs/common/Simulate.py should not notice.
H A Dcluster.pydiff 7716:fa706473bcd5 Fri Oct 22 23:59:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Configs: Stop setting the "mem" parameter in splash2 config files.

This parameter is no longer used, and trying to set it like these scripts were
gives a simobject two parents and causes the simulation to die.
diff 7525:722f2ad014a7 Tue Aug 17 08:06:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once. The C++ Root object already panics if more than one is
created. This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists). It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone. Users who use
configs/common/Simulate.py should not notice.
/gem5/src/arch/alpha/
H A Disa.hhdiff 7703:90299d921559 Sun Oct 10 23:38:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> SPARC: Make SPARC's ISA's clear function initialize everything it should.

Also make it not set some pointers to NULL potentially introducing a memory
leak. That should be done in the constructor.
diff 7702:0e582f3dbc96 Sun Oct 10 23:37:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Alpha: Force all the IPRs to an initial, determinstic value when cleared.
/gem5/src/arch/sparc/
H A Disa.hhdiff 7741:340b6f01d69b Thu Nov 11 05:03:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up some historical style issues.
diff 7703:90299d921559 Sun Oct 10 23:38:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> SPARC: Make SPARC's ISA's clear function initialize everything it should.

Also make it not set some pointers to NULL potentially introducing a memory
leak. That should be done in the constructor.
H A Dasi.hhdiff 7741:340b6f01d69b Thu Nov 11 05:03:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up some historical style issues.
H A Dtlb_map.hhdiff 7741:340b6f01d69b Thu Nov 11 05:03:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up some historical style issues.
/gem5/src/cpu/pred/
H A Dtournament.ccdiff 9480:d059f8a95a42 Thu Jan 24 01:28:00 EST 2013 Nilay Vaish <nilay@cs.wisc.edu>, Timothy Jones <timothy.jones@cl.cam.ac.uk> branch predictor: move out of o3 and inorder cpus
This patch moves the branch predictor files in the o3 and inorder directories
to src/cpu/pred. This allows sharing the branch predictor across different
cpu models.

This patch was originally posted by Timothy Jones in July 2010
but never made it to the repository.
diff 7082:070529b41c1e Thu May 13 23:45:00 EDT 2010 Maximilien Breughe <Maximilien.Breughe@elis.ugent.be> BPRED: Fixed the treshold-bug in the tournament predictor.

Suppose the saturating counters of a branch predictor contain n bits. When the
counter is between 0 and (2^(n-1) - 1), boundaries included, the branch is
predicted as not taken. When the counter is between 2^(n-1) and (2^n - 1),
boundaries included, the branch is predicted as taken.
H A Dras.ccdiff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
/gem5/src/mem/cache/prefetch/
H A DSConscriptdiff 13667:e3ae3619b9ab Tue Feb 05 17:31:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> mem-cache: Added the Delta Correlating Prediction Tables Prefetcher

Reference:
Multi-level hardware prefetching using low complexity delta correlating
prediction tables with partial matching.
Marius Grannaes, Magnus Jahre, and Lasse Natvig. 2010.
In Proceedings of the 5th international conference on High Performance
Embedded Architectures and Compilers (HiPEAC'10)
Change-Id: I7b5d7ede9284862a427cfd5693a47652a69ed49d
Reviewed-on: https://gem5-review.googlesource.com/c/16062
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff 7768:cdb18c1b51ea Fri Nov 19 19:00:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> SCons: Support building without an ISA
/gem5/src/cpu/o3/
H A Dcpu_policy.hhdiff 9480:d059f8a95a42 Thu Jan 24 01:28:00 EST 2013 Nilay Vaish <nilay@cs.wisc.edu>, Timothy Jones <timothy.jones@cl.cam.ac.uk> branch predictor: move out of o3 and inorder cpus
This patch moves the branch predictor files in the o3 and inorder directories
to src/cpu/pred. This allows sharing the branch predictor across different
cpu models.

This patch was originally posted by Timothy Jones in July 2010
but never made it to the repository.
/gem5/src/arch/mips/isa/
H A Dbitfields.isadiff 7799:5d0f62927d75 Mon Dec 20 16:24:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Style: Replace some tabs with spaces.
/gem5/src/arch/x86/
H A Dx86_traits.hhdiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/decoder/
H A Dx87.isadiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Done_byte_opcodes.isadiff 7718:6333e66ce74b Fri Oct 29 05:20:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Make syscalls also serialize after.
diff 7715:5581d0cd2bdb Fri Oct 22 03:24:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Make nop a regular, non-microcoded instruction.

Code in the CPUs that need a nop to carry a fault can't easily deal with a
microcoded nop. This instruction format provides for one that isn't.
diff 7713:ce987fa77797 Fri Oct 22 03:23:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Make syscall instructions non-speculative in SE.
diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/base/
H A Drandom.hhdiff 7771:e10aff32c561 Sat Nov 20 03:12:00 EST 2010 Nathan Binkert <nate@binkert.org> random: small comment about our random number generator and its origin
/gem5/src/dev/arm/
H A Drealview.hh7584:28ddf6d9e982 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add I/O devices for booting linux
H A Drv_ctrl.hh7584:28ddf6d9e982 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add I/O devices for booting linux
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractCacheEntry.ccdiff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass
/gem5/src/mem/slicc/ast/
H A DEnqueueStatementAST.pydiff 7453:1a5db3dd0f62 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.
/gem5/src/arch/arm/isa/insts/
H A Dm5ops.isa7732:a2c660de7787 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for M5 ops in the ARM ISA
/gem5/src/kern/
H A DSConscriptdiff 7768:cdb18c1b51ea Fri Nov 19 19:00:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> SCons: Support building without an ISA
/gem5/src/base/loader/
H A Daout_object.ccdiff 7676:92274350b953 Fri Sep 10 17:58:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: fix sorting of includes and whitespace in some files
/gem5/src/arch/x86/isa/
H A Dspecialize.isadiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly

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