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7741:340b6f01d69b |
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11-Nov-2010 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Clean up some historical style issues.
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4191:c191c1fec061 |
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08-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Panic if any CMT registers are accessed
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add CMT ASI registers src/arch/sparc/tlb.cc: Panic if any of the CMT registers are being accessed
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3825:9b5e6c4d3ecb |
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07-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices
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3824:8900576818d7 |
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06-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Handle access to ASI_QUEUE Add function for interrupt ASIs add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: Add function for interrupt ASIs src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: Add QUEUE asi/misc registers src/arch/sparc/regfile.cc: add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/tlb.cc: Handle access to ASI_QUEUE
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3823:1c8f87aa103e |
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06-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts getting touched.
configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request
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3806:65ae5388c059 |
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29-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Add support for mmapped iprs to atomic cpu
src/arch/SConscript: add mmaped_ipr.hh to switch headers src/arch/sparc/asi.hh: make ASI_IMPLICT=0 so by default nothing needs to be done src/arch/sparc/miscregfile.hh: miscregfile no longer needs to include asi.hh src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: implement panic instructions for mmaped ipr reads src/cpu/simple/atomic.cc: add check for mmaped iprs and handle them if it exists src/mem/request.hh: allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits
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3804:fa7a01dddc7a |
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23-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
first cut at a sparc tlb
src/arch/sparc/SConscript: Add code to serialize/unserialze tlb entries src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: update asi names for how they're listed in the supplement add asis add more asi functions src/arch/sparc/isa_traits.hh: move the interrupt stuff and some basic address space stuff into isa traits src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add mmu registers to tlb get rid of implicit asi stuff... the tlb will handle it src/arch/sparc/regfile.hh: make isnt/dataAsid return ints not asis src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: first cut at sparc tlb src/arch/sparc/vtophys.hh: pagatable nedes to be included here src/mem/request.hh: add asi and if the request is a memory mapped register to the requset object src/sim/host.hh: fix incorrect definition of LL
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3519:83c5c94fb2a8 |
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03-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Fixed a comment
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3123:34edfd0ff545 |
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30-Sep-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Basic work towards supporting ASIs properly
src/arch/sparc/SConscript: Added a file that implements ASI utility functions. These don't go in utility.hh because they aren't supposed to be part of the generic ISA interface. src/arch/sparc/asi.hh: Fixed up some mistranscriptions, and added function prototypes for some ASI utility functions. src/arch/sparc/asi.cc: Implementation of some ASI utility functions.
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3063:479e32cdcdf6 |
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30-Aug-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Forgot some commas
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3062:d95b24c698c3 |
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29-Aug-2006 |
Gabe Black <gblack@eecs.umich.edu> |
ASI constants.
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