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11634:96dee874a9ba |
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15-Sep-2016 |
Ricardo Alves <ricardo.alves@arm.com> |
arm: Add m5_fail support for aarch64
Change-Id: Id2acbc09772be310a0eb9e33295afab07e08a4fa Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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11289:ab19693da8c9 |
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07-Jan-2016 |
Gabor Dozsa <gabor.dozsa@arm.com> |
pseudo inst,util: Add optional key to initparam pseudo instruction
The key parameter can be used to read out various config parameters from within the simulated software.
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10126:943808ead35e |
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23-Mar-2014 |
Eric Van Hensbergen <eric.vanhensbergen@arm.com> |
arm: m5ops readfile64 args broken, offset coming through garbage
There were several sections of the m5ops code which were essentially copy/pasted versions of the 32-bit code. The problem is that some of these didn't account fo4 64-bit registers leading to arguments being in the wrong registers. This patch addresses the args for readfile64, writefile64, and addsymbol64 -- all of which seemed to suffer from a similar set of problems when moving to 64-bit.
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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9687:22e9258c06bb |
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14-May-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
arm: Add support for the m5fail pseudo-op
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9554:406fbcf60223 |
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19-Feb-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
scons: Add warning for missing declarations
This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code.
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8809:bb10807da889 |
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01-Feb-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with head, hopefully the last time for this batch.
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8798:adaa92be9037 |
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16-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge yet again with the main repository.
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8795:0909f8ed7aa0 |
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07-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with main repository.
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8782:10c9297e14d5 |
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02-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Get rid of FULL_SYSTEM in the ARM ISA.
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8734:79592b2b1d55 |
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31-Jan-2012 |
Dam Sunwoo <dam.sunwoo@arm.com> |
util: implements "writefile" gem5 op to export file from guest to host filesystem
Usage: m5 writefile <filename>
File will be created in the gem5 output folder with the identical filename. Implementation is largely based on the existing "readfile" functionality. Currently does not support exporting of folders.
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8733:64a7bf8fa56c |
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31-Jan-2012 |
Geoffrey Blake <geoffrey.blake@arm.com> |
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the O3CPU. These changes have only been tested with the ARM ISA. Other ISAs potentially require modification.
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8659:78f27ef5e919 |
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09-Jan-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for initparam m5 op
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8607:5fb918115c07 |
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31-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
GCC: Get everything working with gcc 4.6.1.
And by "everything" I mean all the quick regressions.
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8555:6fd8d0432d8d |
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19-Sep-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Pseudoinst: Add an initParam pseudo inst function.
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8354:26be660e365a |
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17-Jun-2011 |
Gedare Bloom <gedare@gwmail.gwu.edu> |
ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.
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8204:6c051a8df26a |
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04-Apr-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Fix m5op parameters bug.
All the m5op parameters are 64 bits, but we were only sending 32 bits; and the static register indexes were incorrectly specified.
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8142:e08035e1a1f6 |
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17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
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7732:a2c660de7787 |
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08-Nov-2010 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for M5 ops in the ARM ISA
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