m5ops.isa revision 10126:943808ead35e
15081Sgblack@eecs.umich.edu// 25081Sgblack@eecs.umich.edu// Copyright (c) 2010, 2012-2013 ARM Limited 35081Sgblack@eecs.umich.edu// All rights reserved 45081Sgblack@eecs.umich.edu// 55081Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 65081Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 75081Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 85081Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 95081Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 105081Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 115081Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 125081Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 135081Sgblack@eecs.umich.edu// 145081Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 155081Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 165081Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 175081Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 185081Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 195081Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 205081Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 215081Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 225081Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 235081Sgblack@eecs.umich.edu// this software without specific prior written permission. 245081Sgblack@eecs.umich.edu// 255081Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265081Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275081Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285081Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295081Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305081Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315081Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325081Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335081Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345081Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355081Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365081Sgblack@eecs.umich.edu// 375081Sgblack@eecs.umich.edu// Authors: Gene Wu 385081Sgblack@eecs.umich.edu 395081Sgblack@eecs.umich.edu 405081Sgblack@eecs.umich.edulet {{ 415081Sgblack@eecs.umich.edu header_output = ''' 425081Sgblack@eecs.umich.edu uint64_t join32to64(uint32_t r1, uint32_t r0); 435081Sgblack@eecs.umich.edu ''' 445081Sgblack@eecs.umich.edu decoder_output = ''' 455081Sgblack@eecs.umich.edu uint64_t join32to64(uint32_t r1, uint32_t r0) 465081Sgblack@eecs.umich.edu { 475081Sgblack@eecs.umich.edu uint64_t r = r1; 485081Sgblack@eecs.umich.edu r <<= 32; 495081Sgblack@eecs.umich.edu r |= r0; 505081Sgblack@eecs.umich.edu return r; 515081Sgblack@eecs.umich.edu } 525081Sgblack@eecs.umich.edu ''' 535081Sgblack@eecs.umich.edu exec_output = ''' 545081Sgblack@eecs.umich.edu uint64_t join32to64(uint32_t r1, uint32_t r0); 555081Sgblack@eecs.umich.edu ''' 565081Sgblack@eecs.umich.edu 575081Sgblack@eecs.umich.edu 585081Sgblack@eecs.umich.edu armCode = ''' 595543Ssaidi@eecs.umich.edu PseudoInst::arm(xc->tcBase()); 605081Sgblack@eecs.umich.edu ''' 615543Ssaidi@eecs.umich.edu 625081Sgblack@eecs.umich.edu armIop = InstObjParams("arm", "Arm", "PredOp", 635543Ssaidi@eecs.umich.edu { "code": armCode, 645081Sgblack@eecs.umich.edu "predicate_test": predicateTest }, 655543Ssaidi@eecs.umich.edu ["IsNonSpeculative"]) 665081Sgblack@eecs.umich.edu header_output += BasicDeclare.subst(armIop) 67 decoder_output += BasicConstructor.subst(armIop) 68 exec_output += PredOpExecute.subst(armIop) 69 70 quiesceCode = ''' 71 PseudoInst::quiesce(xc->tcBase()); 72 ''' 73 74 quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp", 75 { "code": quiesceCode, 76 "predicate_test": predicateTest }, 77 ["IsNonSpeculative", "IsQuiesce"]) 78 header_output += BasicDeclare.subst(quiesceIop) 79 decoder_output += BasicConstructor.subst(quiesceIop) 80 exec_output += QuiescePredOpExecute.subst(quiesceIop) 81 82 quiesceNsCode = ''' 83 PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0)); 84 ''' 85 86 quiesceNsCode64 = ''' 87 PseudoInst::quiesceNs(xc->tcBase(), X0); 88 ''' 89 90 quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp", 91 { "code": quiesceNsCode, 92 "predicate_test": predicateTest }, 93 ["IsNonSpeculative", "IsQuiesce"]) 94 header_output += BasicDeclare.subst(quiesceNsIop) 95 decoder_output += BasicConstructor.subst(quiesceNsIop) 96 exec_output += QuiescePredOpExecute.subst(quiesceNsIop) 97 98 quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs64", "PredOp", 99 { "code": quiesceNsCode64, 100 "predicate_test": predicateTest }, 101 ["IsNonSpeculative", "IsQuiesce"]) 102 header_output += BasicDeclare.subst(quiesceNsIop) 103 decoder_output += BasicConstructor.subst(quiesceNsIop) 104 exec_output += QuiescePredOpExecute.subst(quiesceNsIop) 105 106 quiesceCyclesCode = ''' 107 PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0)); 108 ''' 109 110 quiesceCyclesCode64 = ''' 111 PseudoInst::quiesceCycles(xc->tcBase(), X0); 112 ''' 113 114 quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp", 115 { "code": quiesceCyclesCode, 116 "predicate_test": predicateTest }, 117 ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) 118 header_output += BasicDeclare.subst(quiesceCyclesIop) 119 decoder_output += BasicConstructor.subst(quiesceCyclesIop) 120 exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) 121 122 quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles64", "PredOp", 123 { "code": quiesceCyclesCode64, 124 "predicate_test": predicateTest }, 125 ["IsNonSpeculative", "IsQuiesce", "IsUnverifiable"]) 126 header_output += BasicDeclare.subst(quiesceCyclesIop) 127 decoder_output += BasicConstructor.subst(quiesceCyclesIop) 128 exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop) 129 130 quiesceTimeCode = ''' 131 uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase()); 132 R0 = bits(qt_val, 31, 0); 133 R1 = bits(qt_val, 63, 32); 134 ''' 135 136 quiesceTimeCode64 = ''' 137 X0 = PseudoInst::quiesceTime(xc->tcBase()); 138 ''' 139 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp", 140 { "code": quiesceTimeCode, 141 "predicate_test": predicateTest }, 142 ["IsNonSpeculative", "IsUnverifiable"]) 143 header_output += BasicDeclare.subst(quiesceTimeIop) 144 decoder_output += BasicConstructor.subst(quiesceTimeIop) 145 exec_output += PredOpExecute.subst(quiesceTimeIop) 146 147 quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime64", "PredOp", 148 { "code": quiesceTimeCode64, 149 "predicate_test": predicateTest }, 150 ["IsNonSpeculative", "IsUnverifiable"]) 151 header_output += BasicDeclare.subst(quiesceTimeIop) 152 decoder_output += BasicConstructor.subst(quiesceTimeIop) 153 exec_output += PredOpExecute.subst(quiesceTimeIop) 154 155 rpnsCode = ''' 156 uint64_t rpns_val = PseudoInst::rpns(xc->tcBase()); 157 R0 = bits(rpns_val, 31, 0); 158 R1 = bits(rpns_val, 63, 32); 159 ''' 160 161 rpnsCode64 = ''' 162 X0 = PseudoInst::rpns(xc->tcBase()); 163 ''' 164 rpnsIop = InstObjParams("rpns", "Rpns", "PredOp", 165 { "code": rpnsCode, 166 "predicate_test": predicateTest }, 167 ["IsNonSpeculative", "IsUnverifiable"]) 168 header_output += BasicDeclare.subst(rpnsIop) 169 decoder_output += BasicConstructor.subst(rpnsIop) 170 exec_output += PredOpExecute.subst(rpnsIop) 171 172 rpnsIop = InstObjParams("rpns", "Rpns64", "PredOp", 173 { "code": rpnsCode64, 174 "predicate_test": predicateTest }, 175 ["IsNonSpeculative", "IsUnverifiable"]) 176 header_output += BasicDeclare.subst(rpnsIop) 177 decoder_output += BasicConstructor.subst(rpnsIop) 178 exec_output += PredOpExecute.subst(rpnsIop) 179 180 wakeCpuCode = ''' 181 PseudoInst::wakeCPU(xc->tcBase(), join32to64(R1,R0)); 182 ''' 183 184 wakeCpuCode64 = ''' 185 PseudoInst::wakeCPU(xc->tcBase(), X0); 186 ''' 187 188 wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU", "PredOp", 189 { "code": wakeCpuCode, 190 "predicate_test": predicateTest }, 191 ["IsNonSpeculative", "IsUnverifiable"]) 192 header_output += BasicDeclare.subst(wakeCPUIop) 193 decoder_output += BasicConstructor.subst(wakeCPUIop) 194 exec_output += PredOpExecute.subst(wakeCPUIop) 195 196 wakeCPUIop = InstObjParams("wakeCPU", "WakeCPU64", "PredOp", 197 { "code": wakeCpuCode64, 198 "predicate_test": predicateTest }, 199 ["IsNonSpeculative", "IsUnverifiable"]) 200 header_output += BasicDeclare.subst(wakeCPUIop) 201 decoder_output += BasicConstructor.subst(wakeCPUIop) 202 exec_output += PredOpExecute.subst(wakeCPUIop) 203 204 deprecated_ivlbIop = InstObjParams("deprecated_ivlb", "Deprecated_ivlb", "PredOp", 205 { "code": '''warn_once("Obsolete M5 ivlb instruction encountered.\\n");''', 206 "predicate_test": predicateTest }) 207 header_output += BasicDeclare.subst(deprecated_ivlbIop) 208 decoder_output += BasicConstructor.subst(deprecated_ivlbIop) 209 exec_output += PredOpExecute.subst(deprecated_ivlbIop) 210 211 deprecated_ivleIop = InstObjParams("deprecated_ivle", "Deprecated_ivle", "PredOp", 212 { "code": '''warn_once("Obsolete M5 ivle instruction encountered.\\n");''', 213 "predicate_test": predicateTest }) 214 header_output += BasicDeclare.subst(deprecated_ivleIop) 215 decoder_output += BasicConstructor.subst(deprecated_ivleIop) 216 exec_output += PredOpExecute.subst(deprecated_ivleIop) 217 218 deprecated_exit_code = ''' 219 warn_once("Obsolete M5 exit instruction encountered.\\n"); 220 PseudoInst::m5exit(xc->tcBase(), 0); 221 ''' 222 223 deprecated_exitIop = InstObjParams("deprecated_exit", "Deprecated_exit", "PredOp", 224 { "code": deprecated_exit_code, 225 "predicate_test": predicateTest }, 226 ["No_OpClass", "IsNonSpeculative"]) 227 header_output += BasicDeclare.subst(deprecated_exitIop) 228 decoder_output += BasicConstructor.subst(deprecated_exitIop) 229 exec_output += PredOpExecute.subst(deprecated_exitIop) 230 231 m5exit_code = ''' 232 PseudoInst::m5exit(xc->tcBase(), join32to64(R1, R0)); 233 ''' 234 235 m5exit_code64 = ''' 236 PseudoInst::m5exit(xc->tcBase(), X0); 237 ''' 238 239 m5exitIop = InstObjParams("m5exit", "M5exit", "PredOp", 240 { "code": m5exit_code, 241 "predicate_test": predicateTest }, 242 ["No_OpClass", "IsNonSpeculative"]) 243 header_output += BasicDeclare.subst(m5exitIop) 244 decoder_output += BasicConstructor.subst(m5exitIop) 245 exec_output += PredOpExecute.subst(m5exitIop) 246 247 m5fail_code = ''' 248 PseudoInst::m5fail(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 249 ''' 250 m5failIop = InstObjParams("m5fail", "M5fail", "PredOp", 251 { "code": m5fail_code, 252 "predicate_test": predicateTest }, 253 ["No_OpClass", "IsNonSpeculative"]) 254 header_output += BasicDeclare.subst(m5failIop) 255 decoder_output += BasicConstructor.subst(m5failIop) 256 exec_output += PredOpExecute.subst(m5failIop) 257 258 m5exitIop = InstObjParams("m5exit", "M5exit64", "PredOp", 259 { "code": m5exit_code64, 260 "predicate_test": predicateTest }, 261 ["No_OpClass", "IsNonSpeculative"]) 262 header_output += BasicDeclare.subst(m5exitIop) 263 decoder_output += BasicConstructor.subst(m5exitIop) 264 exec_output += PredOpExecute.subst(m5exitIop) 265 266 loadsymbolCode = ''' 267 PseudoInst::loadsymbol(xc->tcBase()); 268 ''' 269 270 loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp", 271 { "code": loadsymbolCode, 272 "predicate_test": predicateTest }, 273 ["No_OpClass", "IsNonSpeculative"]) 274 header_output += BasicDeclare.subst(loadsymbolIop) 275 decoder_output += BasicConstructor.subst(loadsymbolIop) 276 exec_output += PredOpExecute.subst(loadsymbolIop) 277 278 initparamCode = ''' 279 uint64_t ip_val = PseudoInst::initParam(xc->tcBase()); 280 R0 = bits(ip_val, 31, 0); 281 R1 = bits(ip_val, 63, 32); 282 ''' 283 284 initparamCode64 = ''' 285 X0 = PseudoInst::initParam(xc->tcBase()); 286 ''' 287 288 initparamIop = InstObjParams("initparam", "Initparam", "PredOp", 289 { "code": initparamCode, 290 "predicate_test": predicateTest }, 291 ["IsNonSpeculative"]) 292 header_output += BasicDeclare.subst(initparamIop) 293 decoder_output += BasicConstructor.subst(initparamIop) 294 exec_output += PredOpExecute.subst(initparamIop) 295 296 initparamIop = InstObjParams("initparam", "Initparam64", "PredOp", 297 { "code": initparamCode64, 298 "predicate_test": predicateTest }, 299 ["IsNonSpeculative"]) 300 header_output += BasicDeclare.subst(initparamIop) 301 decoder_output += BasicConstructor.subst(initparamIop) 302 exec_output += PredOpExecute.subst(initparamIop) 303 304 resetstats_code = ''' 305 PseudoInst::resetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 306 ''' 307 308 resetstats_code64 = ''' 309 PseudoInst::resetstats(xc->tcBase(), X0, X1); 310 ''' 311 resetstatsIop = InstObjParams("resetstats", "Resetstats", "PredOp", 312 { "code": resetstats_code, 313 "predicate_test": predicateTest }, 314 ["IsNonSpeculative"]) 315 header_output += BasicDeclare.subst(resetstatsIop) 316 decoder_output += BasicConstructor.subst(resetstatsIop) 317 exec_output += PredOpExecute.subst(resetstatsIop) 318 319 resetstatsIop = InstObjParams("resetstats", "Resetstats64", "PredOp", 320 { "code": resetstats_code64, 321 "predicate_test": predicateTest }, 322 ["IsNonSpeculative"]) 323 header_output += BasicDeclare.subst(resetstatsIop) 324 decoder_output += BasicConstructor.subst(resetstatsIop) 325 exec_output += PredOpExecute.subst(resetstatsIop) 326 327 dumpstats_code = ''' 328 PseudoInst::dumpstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 329 ''' 330 331 dumpstats_code64 = ''' 332 PseudoInst::dumpstats(xc->tcBase(), X0, X1); 333 ''' 334 335 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats", "PredOp", 336 { "code": dumpstats_code, 337 "predicate_test": predicateTest }, 338 ["IsNonSpeculative"]) 339 header_output += BasicDeclare.subst(dumpstatsIop) 340 decoder_output += BasicConstructor.subst(dumpstatsIop) 341 exec_output += PredOpExecute.subst(dumpstatsIop) 342 343 dumpstatsIop = InstObjParams("dumpstats", "Dumpstats64", "PredOp", 344 { "code": dumpstats_code64, 345 "predicate_test": predicateTest }, 346 ["IsNonSpeculative"]) 347 header_output += BasicDeclare.subst(dumpstatsIop) 348 decoder_output += BasicConstructor.subst(dumpstatsIop) 349 exec_output += PredOpExecute.subst(dumpstatsIop) 350 351 dumpresetstats_code = ''' 352 PseudoInst::dumpresetstats(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 353 ''' 354 355 dumpresetstats_code64 = ''' 356 PseudoInst::dumpresetstats(xc->tcBase(), X0, X1); 357 ''' 358 359 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats", "PredOp", 360 { "code": dumpresetstats_code, 361 "predicate_test": predicateTest }, 362 ["IsNonSpeculative"]) 363 header_output += BasicDeclare.subst(dumpresetstatsIop) 364 decoder_output += BasicConstructor.subst(dumpresetstatsIop) 365 exec_output += PredOpExecute.subst(dumpresetstatsIop) 366 367 dumpresetstatsIop = InstObjParams("dumpresetstats", "Dumpresetstats64", "PredOp", 368 { "code": dumpresetstats_code64, 369 "predicate_test": predicateTest }, 370 ["IsNonSpeculative"]) 371 header_output += BasicDeclare.subst(dumpresetstatsIop) 372 decoder_output += BasicConstructor.subst(dumpresetstatsIop) 373 exec_output += PredOpExecute.subst(dumpresetstatsIop) 374 375 m5checkpoint_code = ''' 376 PseudoInst::m5checkpoint(xc->tcBase(), join32to64(R1, R0), join32to64(R3, R2)); 377 ''' 378 379 m5checkpoint_code64 = ''' 380 PseudoInst::m5checkpoint(xc->tcBase(), X0, X1); 381 ''' 382 383 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp", 384 { "code": m5checkpoint_code, 385 "predicate_test": predicateTest }, 386 ["IsNonSpeculative", "IsUnverifiable"]) 387 header_output += BasicDeclare.subst(m5checkpointIop) 388 decoder_output += BasicConstructor.subst(m5checkpointIop) 389 exec_output += PredOpExecute.subst(m5checkpointIop) 390 391 m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint64", "PredOp", 392 { "code": m5checkpoint_code64, 393 "predicate_test": predicateTest }, 394 ["IsNonSpeculative", "IsUnverifiable"]) 395 header_output += BasicDeclare.subst(m5checkpointIop) 396 decoder_output += BasicConstructor.subst(m5checkpointIop) 397 exec_output += PredOpExecute.subst(m5checkpointIop) 398 399 m5readfileCode = ''' 400 int n = 4; 401 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 402 R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset); 403 ''' 404 405 m5readfileCode64 = ''' 406 int n = 2; 407 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 408 n = 3; 409 X0 = PseudoInst::readfile(xc->tcBase(), X0, X1, offset); 410 ''' 411 412 m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp", 413 { "code": m5readfileCode, 414 "predicate_test": predicateTest }, 415 ["IsNonSpeculative", "IsUnverifiable"]) 416 header_output += BasicDeclare.subst(m5readfileIop) 417 decoder_output += BasicConstructor.subst(m5readfileIop) 418 exec_output += PredOpExecute.subst(m5readfileIop) 419 420 m5readfileIop = InstObjParams("m5readfile", "M5readfile64", "PredOp", 421 { "code": m5readfileCode64, 422 "predicate_test": predicateTest }, 423 ["IsNonSpeculative", "IsUnverifiable"]) 424 header_output += BasicDeclare.subst(m5readfileIop) 425 decoder_output += BasicConstructor.subst(m5readfileIop) 426 exec_output += PredOpExecute.subst(m5readfileIop) 427 428 m5writefileCode = ''' 429 int n = 4; 430 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 431 n = 6; 432 Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false); 433 R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset, 434 filenameAddr); 435 ''' 436 437 m5writefileCode64 = ''' 438 int n = 2; 439 uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); 440 n = 3; 441 Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false); 442 X0 = PseudoInst::writefile(xc->tcBase(), X0, X1, offset, 443 filenameAddr); 444 ''' 445 446 m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp", 447 { "code": m5writefileCode, 448 "predicate_test": predicateTest }, 449 ["IsNonSpeculative"]) 450 header_output += BasicDeclare.subst(m5writefileIop) 451 decoder_output += BasicConstructor.subst(m5writefileIop) 452 exec_output += PredOpExecute.subst(m5writefileIop) 453 454 m5writefileIop = InstObjParams("m5writefile", "M5writefile64", "PredOp", 455 { "code": m5writefileCode64, 456 "predicate_test": predicateTest }, 457 ["IsNonSpeculative"]) 458 header_output += BasicDeclare.subst(m5writefileIop) 459 decoder_output += BasicConstructor.subst(m5writefileIop) 460 exec_output += PredOpExecute.subst(m5writefileIop) 461 462 m5breakIop = InstObjParams("m5break", "M5break", "PredOp", 463 { "code": "PseudoInst::debugbreak(xc->tcBase());", 464 "predicate_test": predicateTest }, 465 ["IsNonSpeculative"]) 466 header_output += BasicDeclare.subst(m5breakIop) 467 decoder_output += BasicConstructor.subst(m5breakIop) 468 exec_output += PredOpExecute.subst(m5breakIop) 469 470 m5switchcpuIop = InstObjParams("m5switchcpu", "M5switchcpu", "PredOp", 471 { "code": "PseudoInst::switchcpu(xc->tcBase());", 472 "predicate_test": predicateTest }, 473 ["IsNonSpeculative"]) 474 header_output += BasicDeclare.subst(m5switchcpuIop) 475 decoder_output += BasicConstructor.subst(m5switchcpuIop) 476 exec_output += PredOpExecute.subst(m5switchcpuIop) 477 478 m5addsymbolCode = ''' 479 PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2); 480 ''' 481 m5addsymbolCode64 = ''' 482 PseudoInst::addsymbol(xc->tcBase(), X0, X1); 483 ''' 484 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp", 485 { "code": m5addsymbolCode, 486 "predicate_test": predicateTest }, 487 ["IsNonSpeculative"]) 488 header_output += BasicDeclare.subst(m5addsymbolIop) 489 decoder_output += BasicConstructor.subst(m5addsymbolIop) 490 exec_output += PredOpExecute.subst(m5addsymbolIop) 491 492 m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol64", "PredOp", 493 { "code": m5addsymbolCode64, 494 "predicate_test": predicateTest }, 495 ["IsNonSpeculative"]) 496 header_output += BasicDeclare.subst(m5addsymbolIop) 497 decoder_output += BasicConstructor.subst(m5addsymbolIop) 498 exec_output += PredOpExecute.subst(m5addsymbolIop) 499 500 m5panicCode = '''panic("M5 panic instruction called at pc=%#x.", 501 xc->pcState().pc());''' 502 503 m5panicIop = InstObjParams("m5panic", "M5panic", "PredOp", 504 { "code": m5panicCode, 505 "predicate_test": predicateTest }, 506 ["IsNonSpeculative"]) 507 header_output += BasicDeclare.subst(m5panicIop) 508 decoder_output += BasicConstructor.subst(m5panicIop) 509 exec_output += PredOpExecute.subst(m5panicIop) 510 511 m5workbeginCode = '''PseudoInst::workbegin( 512 xc->tcBase(), 513 join32to64(R1, R0), 514 join32to64(R3, R2) 515 );''' 516 517 m5workbeginCode64 = '''PseudoInst::workbegin( 518 xc->tcBase(), 519 X0, 520 X1 521 );''' 522 523 m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp", 524 { "code": m5workbeginCode, 525 "predicate_test": predicateTest }, 526 ["IsNonSpeculative"]) 527 header_output += BasicDeclare.subst(m5workbeginIop) 528 decoder_output += BasicConstructor.subst(m5workbeginIop) 529 exec_output += PredOpExecute.subst(m5workbeginIop) 530 531 m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin64", "PredOp", 532 { "code": m5workbeginCode64, 533 "predicate_test": predicateTest }, 534 ["IsNonSpeculative"]) 535 header_output += BasicDeclare.subst(m5workbeginIop) 536 decoder_output += BasicConstructor.subst(m5workbeginIop) 537 exec_output += PredOpExecute.subst(m5workbeginIop) 538 539 m5workendCode = '''PseudoInst::workend( 540 xc->tcBase(), 541 join32to64(R1, R0), 542 join32to64(R3, R2) 543 );''' 544 545 m5workendCode64 = '''PseudoInst::workend( 546 xc->tcBase(), 547 X0, 548 X1 549 );''' 550 551 m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp", 552 { "code": m5workendCode, 553 "predicate_test": predicateTest }, 554 ["IsNonSpeculative"]) 555 header_output += BasicDeclare.subst(m5workendIop) 556 decoder_output += BasicConstructor.subst(m5workendIop) 557 exec_output += PredOpExecute.subst(m5workendIop) 558 559 m5workendIop = InstObjParams("m5workend", "M5workend64", "PredOp", 560 { "code": m5workendCode64, 561 "predicate_test": predicateTest }, 562 ["IsNonSpeculative"]) 563 header_output += BasicDeclare.subst(m5workendIop) 564 decoder_output += BasicConstructor.subst(m5workendIop) 565 exec_output += PredOpExecute.subst(m5workendIop) 566}}; 567