1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Kevin Lim
30 */
31
32#ifndef __CPU_O3_CPU_POLICY_HH__
33#define __CPU_O3_CPU_POLICY_HH__
34
35#include "cpu/o3/comm.hh"
36#include "cpu/o3/commit.hh"
37#include "cpu/o3/decode.hh"
38#include "cpu/o3/fetch.hh"
39#include "cpu/o3/free_list.hh"
40#include "cpu/o3/iew.hh"
41#include "cpu/o3/inst_queue.hh"
42#include "cpu/o3/lsq.hh"
43#include "cpu/o3/lsq_unit.hh"
44#include "cpu/o3/mem_dep_unit.hh"
45#include "cpu/o3/regfile.hh"
46#include "cpu/o3/rename.hh"
47#include "cpu/o3/rename_map.hh"
48#include "cpu/o3/rob.hh"
49#include "cpu/o3/store_set.hh"
50
51/**
52 * Struct that defines the key classes to be used by the CPU.  All
53 * classes use the typedefs defined here to determine what are the
54 * classes of the other stages and communication buffers.  In order to
55 * change a structure such as the IQ, simply change the typedef here
56 * to use the desired class instead, and recompile.  In order to
57 * create a different CPU to be used simultaneously with this one, see
58 * the alpha_impl.hh file for instructions.
59 */
60template<class Impl>
61struct SimpleCPUPolicy
62{
63    /** Typedef for the freelist of registers. */
64    typedef UnifiedFreeList FreeList;
65    /** Typedef for the rename map. */
66    typedef UnifiedRenameMap RenameMap;
67    /** Typedef for the ROB. */
68    typedef ::ROB<Impl> ROB;
69    /** Typedef for the instruction queue/scheduler. */
70    typedef InstructionQueue<Impl> IQ;
71    /** Typedef for the memory dependence unit. */
72    typedef ::MemDepUnit<StoreSet, Impl> MemDepUnit;
73    /** Typedef for the LSQ. */
74    typedef ::LSQ<Impl> LSQ;
75    /** Typedef for the thread-specific LSQ units. */
76    typedef ::LSQUnit<Impl> LSQUnit;
77
78    /** Typedef for fetch. */
79    typedef DefaultFetch<Impl> Fetch;
80    /** Typedef for decode. */
81    typedef DefaultDecode<Impl> Decode;
82    /** Typedef for rename. */
83    typedef DefaultRename<Impl> Rename;
84    /** Typedef for Issue/Execute/Writeback. */
85    typedef DefaultIEW<Impl> IEW;
86    /** Typedef for commit. */
87    typedef DefaultCommit<Impl> Commit;
88
89    /** The struct for communication between fetch and decode. */
90    typedef DefaultFetchDefaultDecode<Impl> FetchStruct;
91
92    /** The struct for communication between decode and rename. */
93    typedef DefaultDecodeDefaultRename<Impl> DecodeStruct;
94
95    /** The struct for communication between rename and IEW. */
96    typedef DefaultRenameDefaultIEW<Impl> RenameStruct;
97
98    /** The struct for communication between IEW and commit. */
99    typedef DefaultIEWDefaultCommit<Impl> IEWStruct;
100
101    /** The struct for communication within the IEW stage. */
102    typedef ::IssueStruct<Impl> IssueStruct;
103
104    /** The struct for all backwards communication. */
105    typedef TimeBufStruct<Impl> TimeStruct;
106
107};
108
109#endif //__CPU_O3_CPU_POLICY_HH__
110